參數(shù)資料
型號： MSC8103M1200F
廠商： MOTOROLA INC
元件分類： 數(shù)字信號處理
英文描述： 64-BIT, 75 MHz, OTHER DSP, PBGA332
封裝： 17 X 17 MM, FLIP-CHIP, PLASTIC, BGA-332
文件頁數(shù)： 82/120頁
文件大?。?/td> 1952K
代理商： MSC8103M1200F
2-14
AC Timings
Table 2-16. AC Timing for SIU Inputs
No.
Characteristic
Value2
Units
10
Hold time for all signals after the 50% level of the REFCLK rising edge
0.5
ns
11a
ABB/AACK setup time before the 50% level of the REFCLK rising edge
3.5
ns
11b
DBG/DBB/BR/TC setup time before the 50% level of the REFCLK rising edge
5.0
ns
11c
ARTRY setup time before the 50% level of the REFCLK rising edge
4.0
ns
11d
TA setup time before the 50% level of the REFCLK rising edge
Pipeline mode
Non-pipeline mode
3.5
4.0
ns
11e
TEA setup time before the 50% level of the REFCLK rising edge
Pipeline mode
Non-pipeline mode
4.0
3.0
ns
11f
PSDVAL setup time before the 50% level of the REFCLK rising edge
Pipeline mode
Non-pipeline mode
3.5
ns
11g
TS setup time before the 50% level of the REFCLK rising edge
5.0
ns
11h
BG setup time before the 50% level of the REFCLK rising edge
4.5
ns
12
Data bus setup time before the 50% level of the REFCLK rising edge in Normal
Pipeline mode
Non-pipeline mode
2.5
5.0
ns
13
Data bus setup time before the 50% level of the REFCLK rising edge in ECC and
PARITY modes
Pipeline mode
Non-pipeline mode
2.5
8.0
ns
14
DP setup time before the 50% level of the REFCLK rising edge
Pipeline mode
Non-pipeline mode
4.0
9.0
ns
15a
Address bus setup time before the 50% level of the REFCLK rising edge
Extra cycle mode (SIUBCR[EXDD] = 0)
Non-extra cycle mode (SIUBCR[EXDD] = 1)
5.0
8.0
ns
15b
Address attributes: TT/TBST/TSIZ/GBL setup time before the 50% level of the
REFCLK rising edge
Extra cycle mode (SIUBCR[EXDD] = 0)
Non-extra cycle mode (SIUBCR[EXDD] = 1)
5.0
5.5
ns
161
PUPMWAIT/IRQ signals Setup time before the 50% level of the REFCLK rising edge
3.0
ns
Notes:
1.
The setup time for these signals is for synchronous operation. Any setup time can be used for
asynchronous operation.
2.
Input specifications are measured from the 50% level of the rising edge of REFCLK to the 50% level of
the signal. Timings are measured at the pin.
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