參數(shù)資料
型號： MSC8103M1200F
廠商： MOTOROLA INC
元件分類： 數(shù)字信號處理
英文描述： 64-BIT, 75 MHz, OTHER DSP, PBGA332
封裝： 17 X 17 MM, FLIP-CHIP, PLASTIC, BGA-332
文件頁數(shù)： 64/120頁
文件大小： 1952K
代理商： MSC8103M1200F
1-44
JTAG Test Access Port Signals
1.8 JTAG Test Access Port Signals
The MSC8103 supports the standard set of Test Access Port (TAP) signals defined by IEEE 1149.1
Standard Test Access Port and Boundary-Scan Architecture specification and described in Table 1-11.
PD7
SMC1: SMSYN
FCC1: TXADDR3
UTOPIA master
FCC1: TXADDR3
UTOPIA slave
FCC1: TXCLAV2
UTOPIA multi-PHY master,
direct polling
Input
Output
Input
SMC1: Serial Management Synchronization
Supported by SMC1. SMSYN is an input. The SMC
interface consists of SMTXD, SMRXD, SMSYN and a clock.
Not all signals are used for all applications. SMCs are
full-duplex ports that supports three protocols or modes:
UART, transparent or general-circuit interface (GCI).
FCC1: UTOPIA Master Transmit Address Bit 3
In the ATM UTOPIA master interface supported by FCC1
using multiplexed polling, this is transmit address bit 3.
FCC1: UTOPIA Slave Transmit Cell Available 2
In the ATM UTOPIA slave interface supported by FCC1
using multiplexed polling, this is transmit address bit 3.
FCC1: UTOPIA Multi-PHY Master Transmit Cell
Available 2 Direct Polling
In the ATM UTOPIA master interface supported by FCC1
using direct polling, TXCLAV2 is asserted by an external
UTOPIA slave PHY to indicate that it can accept one
complete ATM cell.
Table 1-11. JTAG Test Access Port Signals
Signal
Name
Type
Signal Description
TCK
Input
Test Clock—A test clock signal for synchronizing JTAG test logic.
TDI
Input
Test Data Input—A test data serial signal for test instructions and data. TDI is sampled
on the rising edge of TCK and has an internal pull-up resistor.
TDO
Output
Test Data Output—A test data serial signal for test instructions and data. TDO can be
tri-stated. The signal is actively driven in the shift-IR and shift-DR controller states and
changes on the falling edge of TCK.
TMS
Input
Test Mode Select—Sequences the test controller’s state machine, is sampled on the
rising edge of TCK, and has an internal pull-up resistor.
TRST
Input
Test Reset—Asynchronously initializes the test controller, has an internal pull-up
resistor, and must be asserted after power up.
Table 1-10. Port D Signals (Continued)
Name
Dedicated
I/O Data
Direction
Description
General-
Purpose
I/O
Peripheral Controller:
Dedicated I/O
Protocol
相關(guān)PDF資料
PDF描述
MSC8103M1100F 64-BIT, 68.75 MHz, OTHER DSP, PBGA332
MSC8154SVT1000B 0-BIT, OTHER DSP, PBGA783
MSC8154TVT1000B 0-BIT, OTHER DSP, PBGA783
MSC8156ESVT1000B 0-BIT, OTHER DSP, PBGA783
MSC8156ETVT1000B 0-BIT, OTHER DSP, PBGA783
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MSC8103RM/D 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Network Digital Signal Processor
MSC8103VT1100F 功能描述:IC DSP 16BIT 275MHZ 332-FCPBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:StarCore 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤
MSC8103VT1200F 功能描述:IC DSP 16BIT 300MHZ 332-FCPBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:StarCore 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤
MSC81058 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:RF & MICROWAVE TRANSISTORS GENERAL PURPOSE AMPLIFIER APPLICATIONS
MSC81090 制造商:ASI 制造商全稱:ASI 功能描述:NPN SILICON RF POWER TRANSISTOR
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*