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參數(shù)資料
| 型號(hào)： | MSC8103M1200F |
| 廠商： | MOTOROLA INC |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | 64-BIT, 75 MHz, OTHER DSP, PBGA332 |
| 封裝： | 17 X 17 MM, FLIP-CHIP, PLASTIC, BGA-332 |
| 文件頁數(shù)： | 26/120頁 |
| 文件大?。?/td> | 1952K |
| 代理商： | MSC8103M1200F |
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1-9
System Bus, HDI16, and Interrupt Signals
Reserved
BADDR29
IRQ2
Output
Input
The primary configuration is reserved.
Burst Address 29
1
One of five outputs of the memory controller. These pins connect directly to
memory devices controlled by the MSC8103 memory controller.
Interrupt Request 21
One of eight external lines that can request a service routine, via the internal
interrupt controller, from the SC140 core.
Reserved
BADDR30
IRQ3
Output
Input
The primary configuration is reserved.
Burst Address 30
1
One of five outputs of the memory controller. These pins connect directly to
memory devices controlled by the MSC8103 memory controller.
Interrupt Request 31
One of eight external lines that can request a service routine, via the internal
interrupt controller, from the SC140 core.
Reserved
BADDR31
IRQ5
Output
Input
The primary configuration is reserved.
Burst Address 31
1
One of five outputs of the memory controller. These pins connect directly to
memory devices controlled by the MSC8103 memory controller.
Interrupt Request 51
One of eight external lines that can request a service routine, via the internal
interrupt controller, from the SC140 core.
BR
Input/Output
Output
Input
Bus Request2
An output when an external arbiter is used. The MSC8103 asserts this pin to
request ownership of the bus.
An input when an internal arbiter is used. An external master should assert this pin
to request bus ownership from the internal arbiter.
BG
Input/Output
Output
Input
Bus Grant2
An output when an internal arbiter is used. The MSC8103 asserts this pin to grant
bus ownership to an external bus master.
An input when an external arbiter is used. The external arbiter should assert this
pin to grant bus ownership to the MSC8103.
ABB
IRQ2
Input/Output
Output
Input
Address Bus Busy1
The MSC8103 asserts this pin for the duration of the address bus tenure. Following
an address acknowledge (AACK) signal, which terminates the address bus tenure,
the MSC8103 deasserts ABB for a fraction of a bus cycle and then stops driving
this pin.
The MSC8103 does not assume bus ownership as long as it senses that this pin is
asserted by an external bus master.
Interrupt Request 21
One of the eight external lines that can request a service routine, via the internal
interrupt controller, from the SC140 core.
Table 1-5.
System Bus, HDI16, and Interrupt Signals (Continued)
Signal
Data Flow
Description
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