參數(shù)資料
型號: MSC8103M1200F
廠商: MOTOROLA INC
元件分類: 數(shù)字信號處理
英文描述: 64-BIT, 75 MHz, OTHER DSP, PBGA332
封裝: 17 X 17 MM, FLIP-CHIP, PLASTIC, BGA-332
文件頁數(shù): 1/120頁
文件大?。?/td> 1952K
代理商: MSC8103M1200F
Technical Data
MSC8103/D
Rev. 5 , 10/2003
Networking Digital
Signal Processor
(mask set 2K87M)
Figure 1. MSC8103 Block Diagram
UTOPIA
Other
Peripherals
MII
TDMs
CPM
M
CC
/
UA
RT
/
HDL
C
/
T
ra
n
s
p
a
re
n
t
/
E
ther
net
/
F
a
s
tE
ther
net
/A
T
M
/
S
C
PIT
System Protection
Reset Control
Clock Control
SIU
8/16-bit
Host
SC140
Power
Management
Clock/PLL
64-bit XA Data Bus
128-bit P-Bus
64-bit XB Data Bus
Extended Core
Interface
64-bit Local Bus
64-bit System Bus
Core
S
e
ri
al
Inter
fac
e
and
T
S
A
3
× FCC
4
× SCC
SPI
I2C
2
× MCC
2
× SMC
Interrupt
Timers
Baud Rate
Parallel I/O
Generators
Controller
Dual Ported
RAM
Program
Sequencer
Address
Register
File
Data ALU
Register
File
Address
ALU
Data
ALU
64/32-bit
System
Bus
Interrupts
EOnCE
JTAG
2
× SDMA
RISC
Interface
DMA
Engine
Bridge
Q2PPC
Bridge
Boot
ROM
SRAM
512 KB
128-bit QBus
MEMC
L1 Interface
HDI16
MEMC
{
PIC
SIC_EXT
SIC
Interrupts
The Motorola
MSC8103 16-bit
Digital Signal
Processor (DSP) is the
first member of the
family of DSPs based
on the SC140 DSP
core. The MSC8103 is
offered in two core
speed levels: 275 and
300 MHz.
The Motorola MSC8103 DSP is a very versatile
device that integrates the high-performance SC140
four-ALU (Arithmetic Logic Unit) DSP core along
with 512 KB of internal memory, a
Communications Processor Module (CPM), a
64-bit bus, a very flexible System Integration Unit
(SIU), and a 16-channel DMA engine on a single
device. With its four-ALU core, the MSC8103 can
execute up to four multiply-accumulate (MAC)
operations in a single clock cycle. The MSC8103
CPM is a 32-bit RISC-based communications
protocol engine that can network to Time-Division
Multiplexed (TDM) highways, Ethernet, and
Asynchronous Transfer mode (ATM) backbones.
The MSC8103 60x-compatible bus interface
facilitates its connection to multi-master system
architectures. The very large internal memory, 512
KB, reduces the need for external program and
data memories. The MSC8103 offers 1200 DSP
MMACS performance using an internal 300 MHz
clock with a 1.6 V core and independent 3.3 V
input/output (I/O). Figure 1 shows a block
diagram of the MSC8103 processor.
What’s New?
Rev. 5 includes the
following changes:
Added note for DLLIN
when DLL is disabled
Added output
impedances in Table
2-9 and renumbered
subsequent tables.
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