參數(shù)資料
型號： MSC8103M1200F
廠商： MOTOROLA INC
元件分類： 數(shù)字信號處理
英文描述： 64-BIT, 75 MHz, OTHER DSP, PBGA332
封裝： 17 X 17 MM, FLIP-CHIP, PLASTIC, BGA-332
文件頁數(shù)： 71/120頁
文件大?。?/td> 1952K
代理商： MSC8103M1200F
2-4
Clock Configuration
2.6 Clock Configuration
The following sections provide a general description of clock configuration.
2.6.1 Valid Clock Modes
Table 2-6 shows the maximum frequency values for each rated core frequency (275 or 300 MHz). The
user must ensure that maximum frequency values are not exceeded.
Six bit values map the MSC8103 clocks to one of the valid configuration mode options. Each option
determines the CLKIN, SC140 core, system bus, SCC clock, CPM, and CLKOUT frequencies. The six bit
values are derived from three dedicated input pins (MODCK[1–3]) and three bits from the hard reset
configuration word (MODCK_H). To configure the SPLL pre-division factor, SPLL multiplication
factor, and the frequencies for the SC140 core, SCC clocks, CPM parallel I/O ports, and system buses,
the MODCK[1–3] pins are sampled and combined with the MODCK_H values when the internal
power-on reset (internal PORESET) is deasserted. Clock configuration changes only when the internal
PORESET
signal is deasserted. The following factors are configured:
SPLL pre-division factor (SPLL PDF)
SPLL multiplication factor (SPLL MF)
Bus post-division factor (Bus DF)
CPM division factor (CPM DF)
Core division factor (Core DF)
CPLL pre-division factor (CPLL PDF)
CPLL multiplication factor (CPLL MF)
The SCC division factor (SCC DF) is fixed at 4. The BRG division factor (BRG DF) is configured
through the System Clock Control Register (SCCR) and can be 4, 16 (default after reset), 64, or 256.
Note:
Refer to AN2306/D Clock Mode Selection for MSC8101 and MSC8103 Mask Set 2K87M for
details on clock configuration.
Table 2-5. Typical Power Dissipation
Characteristic
Symbol
Typical
Unit
Core power dissipation at 300 MHz
PCORE
450
mW
CPM power dissipation at 200 MHz
PCPM
320
mW
SIU power dissipation at 100 MHz
PSIU
80
mW
Core leakage power
PLCO
3mW
CPM leakage power
PLCP
6mW
SIU leakage power
PLSI
2mW
Table 2-6. Maximum Frequencies
Characteristic
Maximum Frequency in MHz
Core Frequency
275
300
CPM Frequency (CPMCLK)
183.33
200
Bus Frequency (BCLK)
91.67
100
Serial Communication Controller Clock Frequency (SCLK)
91.67
100
Baud Rate Generator Clock Frequency (BRGCLK)
91.67
100
External Clock Output Frequency (CLKOUT)
91.67
100
相關PDF資料
PDF描述
MSC8103M1100F 64-BIT, 68.75 MHz, OTHER DSP, PBGA332
MSC8154SVT1000B 0-BIT, OTHER DSP, PBGA783
MSC8154TVT1000B 0-BIT, OTHER DSP, PBGA783
MSC8156ESVT1000B 0-BIT, OTHER DSP, PBGA783
MSC8156ETVT1000B 0-BIT, OTHER DSP, PBGA783
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