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參數(shù)資料
| 型號： | MPC604ERX300XX |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | RISC PROCESSOR, CBGA255 |
| 封裝： | 21 X 21 MM, 3.30 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-255 |
| 文件頁數(shù)： | 28/29頁 |
| 文件大小： | 217K |
| 代理商： | MPC604ERX300XX |
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PRELIMINAR
Y
8
PID9q-604e Hardware Specifications
PRELIMINARYSUBJECT TO CHANGE WITHOUT NOTICE
Table 5 provides the power consumption for the 604e.
1.4.2 AC Electrical Characteristics
This section provides the AC electrical characteristics for the 604e. These specications are for 266, 300,
and 333 MHz processor core frequencies. The processor core frequency is determined by the bus
(SYSCLK) frequency and the settings of the PLL_CFG[03] signals. All timings are specied respective to
the rising edge of SYSCLK.
1.4.2.1 Clock AC Specications
Table 6 provides the clock AC timing specications as dened in Figure 1.
Table 5. Power Consumption
CPU Clock:
SYSCLK
Processor Core Frequency
Unit
266 MHz
300 MHz
333 MHz
Full-On Mode
Typical
Maximum
6.0
6.8
7.5
W
10.6
12.0
13.4
W
Nap Mode
Typical
Maximum
TBD
W
0.78
0.80
0.82
W
Notes:
1. These values apply for all valid PLL_CFG[03] settings and do not include output
driver power (OVdd) or analog supply power (AVdd). OVdd power is system
dependent but is typically
10% of Vdd. Worst-case AVdd = 15 mW.
2. Typical power is an average value estimated at Vdd = AVdd = 1.9 V, OVdd = 3.3 V, Tj =
25 C in a system executing typical applications and benchmark sequences. Typical
power numbers should be used in planning for proper thermal management.
3. Maximum power is estimated at Vdd = AVdd = 2.0 V, OVdd = 3.465 V,Tj = 0 C using a
worst-case instruction mix. These values should be used for power supply design.
4. Nap mode power consumption is estimated, and assumes no snoop activity.
Table 6. Clock AC Timing Specifications
Vdd = AVdd = 1.9 ±100 mV dc, OVdd = 3.3 ± 5% V dc, GND = 0 V dc, 0
Tj 105 C
Num
Characteristic
266 MHz
300 MHz
333 MHz
Unit
Notes
Min
Max
Min
Max
Min
Max
Processor frequency
250
266
300
333
MHz
1
VCO frequency
500
532
600
666
MHz
1
SYSCLK frequency
35.7
100
38
100
42.9 100
MHz
1, 6
1
SYSCLK cycle time
10
35
10
28
10
25
ns
2, 3
SYSCLK rise and fall time
1.0
2.0
1.0
2.0
1.0
2.0
ns
2
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