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參數(shù)資料
| 型號： | MPC604ERX300XX |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | RISC PROCESSOR, CBGA255 |
| 封裝： | 21 X 21 MM, 3.30 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-255 |
| 文件頁數(shù)： | 23/29頁 |
| 文件大?。?/td> | 217K |
| 代理商： | MPC604ERX300XX |
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PRELIMINAR
Y
PID9q-604e Hardware Specifications
3
PRELIMINARYSUBJECT TO CHANGE WITHOUT NOTICE
Seven independent execution units and two register les
BPU featuring dynamic branch prediction
Two-entry reservation station
Out-of-order execution through two branches
Shares dispatch bus with CRU
64-entry fully-associative branch target address cache (BTAC). In the 604e, the BTAC can
be disabled and invalidated.
512-entry branch history table (BHT) with two bits per entry for four levels of prediction
not-taken, strongly not-taken, taken, strongly taken
Condition register logical unit
Two-entry reservation station
Shares dispatch bus with BPU
Two single-cycle IUs (SCIUs) and one multiple-cycle IU (MCIU)
Instructions that execute in the SCIU take one cycle to execute; most instructions that
execute in the MCIU take multiple cycles to execute.
Each SCIU has a two-entry reservation station to minimize stalls
The MCIU has a single-entry reservation station and provides early exit (three cycles) for
16- x 32-bit and overow operations.
Thirty-two GPRs for integer operands
Three-stage oating-point unit (FPU)
Fully IEEE 754-1985-compliant FPU for both single- and double-precision operations
Supports non-IEEE mode for time-critical operations
Fully pipelined, single-pass double-precision design
Hardware support for denormalized numbers
Two-entry reservation station to minimize stalls
Thirty-two 64-bit FPRs for single- or double-precision operands
Load/store unit (LSU)
Two-entry reservation station to minimize stalls
Single-cycle, pipelined cache access
Dedicated adder performs effective address (EA) calculations
Performs alignment and precision conversion for oating-point data
Performs alignment and sign extension for integer data
Four-entry nish load queue (FLQ) provides load miss buffering
Six-entry store queue
Supports both big- and little-endian modes
Rename buffers
Twelve GPR rename buffers
Eight FPR rename buffers
Eight condition register (CR) rename buffers
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