參數(shù)資料
型號(hào)： MPC604ERX300XX
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： RISC PROCESSOR, CBGA255
封裝： 21 X 21 MM, 3.30 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-255
文件頁(yè)數(shù)： 12/29頁(yè)
文件大?。?/td> 217K
代理商： MPC604ERX300XX
PRELIMINAR
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PID9q-604e Hardware Specifications
PRELIMINARYSUBJECT TO CHANGE WITHOUT NOTICE
1.1 Overview
The 604e is an implementation of the PowerPC family of reduced instruction set computing (RISC)
microprocessors. The 604e implements the PowerPC architecture as it is specied for 32-bit addressing,
which provides 32-bit effective (logical) addresses, integer data types of 8, 16, and 32 bits, and oating-
point data types of 32 and 64 bits (single-precision and double-precision). For 64-bit PowerPC
implementations, the PowerPC architecture provides additional 64-bit integer data types, 64-bit addressing,
and related features.
The 604e is a superscalar processor capable of issuing four instructions simultaneously. As many as seven
instructions can nish execution in parallel. The 604e has seven execution units that can operate in
parallela oating-point unit (FPU), a branch processing unit (BPU), a condition register unit (CRU), a
load/store unit (LSU), and three integer units (IUs)two single-cycle integer units (SCIUs) and one
multiple-cycle integer unit (MCIU).
This parallel design, combined with the PowerPC architectures specication of uniform instructions that
allows for rapid execution times, yields high efciency and throughput. The 604es rename buffers,
reservation stations, dynamic branch prediction, and completion unit increase instruction throughput,
guarantee in-order completion, and ensure a precise exception model. (Note that the PowerPC architecture
specication refers to all exceptions as interrupts.)
The 604e has separate memory management units (MMUs) and separate 32-Kbyte on-chip caches for
instructions and data. The 604e implements two 128-entry, two-way set associative translation lookaside
buffers (TLBs), one for instructions and one for data, and provides support for demand-paged virtual
memory address translation and variable-sized block translation. The TLBs and the cache use least-recently
used (LRU) replacement algorithms.
The 604e has a 64-bit external data bus and a 32-bit address bus. The 604e interface protocol allows multiple
masters to compete for system resources through a central external arbiter. Additionally, on-chip snooping
logic maintains data cache coherency for multiprocessor applications. The 604e supports single-beat and
burst data transfers for memory accesses and memory-mapped I/O accesses.
The 604e uses an advanced, 1.9V CMOS process technology and is fully compatible with 3.3V TTL
devices.
1.2 Features
This section summarizes features of the 604es implementation of the PowerPC architecture. Major features
of the 604e are as follows:
High-performance, superscalar microprocessor
As many as four instructions can be issued per clock
As many as seven instructions can start executing per clock (including three integer
instructions)
Single-clock-cycle execution for most instructions
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