
PRELIMINAR
Y
PID9q-604e Hardware Specifications
5
PRELIMINARYSUBJECT TO CHANGE WITHOUT NOTICE
Four burst write queuesthree for cache copyback operations and one for snoop push
operations
Two single-beat write queues
Additional signals and signal redenition for direct-store operations
Provides a data streaming mode that allows consecutive burst read data transfers to occur
without intervening dead cycles. This mode also disables data retry operations.
No-DRTRY mode eliminates the DRTRY signal from the qualied bus grant and allows read
operations. This improves performance on read operations for systems that do not use the
DRTRY signal. No-DRTRY mode makes read data available to the processor one bus clock
cycle sooner than if normal mode is used.
Multiprocessing support features include the following:
Hardware enforced, four-state cache coherency protocol (MESI) for data cache. Bits are
provided in the instruction cache to indicate only whether a cache block is valid or invalid.
Separate port into data cache tags for bus snooping
Load/store with reservation instruction pair for atomic memory references, semaphores, and
other multiprocessor operations
Power management
NAP mode supports full shut down and snooping
Operating voltage of 1.9 ± 100 mV
Performance monitor can be used to help in debugging system designs and improving software
efciency, especially in multiprocessor systems.
In-system testability and debugging features through JTAG boundary-scan capability
1.3 General Parameters
The following list provides a summary of the general parameters of the 604e:
Technology
0.25 m CMOS, ve-layer metal
Die size
6.97 mm x 6.75mm (47 mm2)
Transistor count
5.1 million
Logic design
Fully-static
Package
Surface mount 255-lead ceramic ball grid array (CBGA)
Core power supply
1.9 V ± 100 mV dc
I/O power supply
3.3 V ± 5% V dc