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參數(shù)資料
| 型號： | MPC604ERX300XX |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | RISC PROCESSOR, CBGA255 |
| 封裝： | 21 X 21 MM, 3.30 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-255 |
| 文件頁數(shù)： | 13/29頁 |
| 文件大?。?/td> | 217K |
| 代理商： | MPC604ERX300XX |
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PRELIMINAR
Y
20
PID9q-604e Hardware Specifications
PRELIMINARYSUBJECT TO CHANGE WITHOUT NOTICE
1.7.0.1 Mechanical Dimensions of the CBGA Package
Figure 10 provides the mechanical dimensions and bottom surface nomenclature of the IBM and Motorola
CBGA package.
Figure 10. Mechanical Dimensions and Bottom Surface Nomenclature of the CBGA Package
1.8 System Design Information
This section provides electrical and thermal design recommendations for successful application of the 604e.
1.8.1 PLL Conguration
The 604e PLL is congured by the PLL_CFG[03] signals. For a given SYSCLK (bus) frequency, the PLL
conguration signals set the internal CPU and VCO frequency of operation. The PLL conguration for the
604e is shown in Table 11 for nominal frequencies.
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. DIMENSIONS IN MILLIMETERS.
3. TOP SIDE A1 CORNER INDEX IS A METALIZED
FEATURE WITHVARIOUS SHAPES.BOTTOM SIDE
A1CORNERISDESIGNATEDWITHABALLMISSING
FROM THE ARRAY.
0.2
B
C
255X
D
2X
A1 CORNER
E
e
E1
D1
0.2
2X
B
A
123456789 10 11 12 13 14 15 16
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
e/2
A
0.3
C
0.15
b
e/2
A
A1
A2
C
0.15 C
Millimeters
DIM
MIN
MAX
A
2.50
3.30
A1
0.79
0.99
A2
1.00
1.40
b
0.82
0.93
D
21.00 BSC
D1
5.00
16.00
e
1.27 BSC
E
21.00 BSC
E1
5.00
16.00
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