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參數(shù)資料
| 型號(hào)： | MPC604ERX300XX |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | RISC PROCESSOR, CBGA255 |
| 封裝： | 21 X 21 MM, 3.30 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-255 |
| 文件頁數(shù)： | 2/29頁 |
| 文件大?。?/td> | 217K |
| 代理商： | MPC604ERX300XX |
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PRELIMINAR
Y
10
PID9q-604e Hardware Specifications
PRELIMINARYSUBJECT TO CHANGE WITHOUT NOTICE
1.4.2.2 Input AC Specications
Table 7 provides the input AC timing specications for the 604e as dened in Figure 2. These specications
are for 266, 300, and 333 MHz processor core frequencies.
Figure 2 provides the input timing diagram for the 604e.
Figure 2. Input Timing Diagram
Table 7. Input AC Timing Specifications1
Vdd = AVdd = 1.9 ±100 mV dc, OVdd = 3.3 ± 5% V dc, GND = 0 V dc, 0
Tj 105 C
Num
Characteristic
266, 300, 333 MHz
Unit
Notes
Min
Max
7a
ARTRY, SHD, ABB, TS, XATS, AACK,BG, DRTRY, TA, DBG,
DBB, TEA, DBDIS, and DBWO valid to SYSCLK (input setup)
3.50
ns
7b
All other inputs valid to SYSCLK (input setup)7
2.50
ns
2
8
SYSCLK to all inputs invalid (input hold)
ns
9
Mode select input valid to HRESET (input setup for DRTRY)
8 * tsysclk
ns
3, 4, 5,
6
10
HRESET to mode select input invalid (input hold for DRTRY)
0.5
ns
3, 4, 5,
6
Notes:
1. Input specications are measured from the TTL level (0.8 or 2.0 V) of the signal in question to the 0.9 V of
the rising edge of the input SYSCLK. Input and output timings are measured at the pin (see Figure 2).
2. All other input signals include the following signalsall inputs except ARTRY, SHD, ABB, TS, XATS, AACK,
BG, DRTRY, TA, DBG, DBB, DBWO, DBDIS, TEA, and JTAG inputs.
3. The setup and hold time is with respect to the rising edge of HRESET (see Figure 3).
4. tsysclk is the period of the external clock (SYSCLK) in nanoseconds.
5. These values are guaranteed by design, and are not tested.
6. Note this is for conguration of the fast-L2 mode and the no-DRTRY mode.
7. Setup time is extended by 0.5 ns for these signals when Hysteresis On mode is enabled.
VM
SYSCLK
ALL INPUTS
VM = Midpoint Voltage (0.9 V)
7
8
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