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參數(shù)資料
| 型號(hào)： | MPC5200VR400BR2 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 400 MHz, MICROPROCESSOR, PBGA272 |
| 封裝： | 27 X 27 MM, 1.27 MM PITCH, ROHS COMPLIANT, PLASTIC, BGA-272 |
| 文件頁數(shù)： | 64/72頁 |
| 文件大?。?/td> | 978K |
| 代理商： | MPC5200VR400BR2 |
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MPC5200B Data Sheet, Rev. 4
Freescale Semiconductor
67
Normally this interface is implemented, using a COP (common on-chip processor) connector. The COP allows a remote
computer system (typically, a PC with dedicated hardware and debugging software) to access and control the internal operations
of the MPC5200B.
3.4.2
e300 COP/BDM Interface
There are two possibilities to connect the JTAG interface: using it with a COP connector and without a COP connector.
3.4.2.1
Boards Interfacing the JTAG Port via a COP Connector
The MPC5200B functional pin interface and internal logic provides access to the embedded e300 processor core through the
Freescale (formerly Motorola) standard COP/BDM interface. Table 53 gives the COP/BDM interface signals. The pin order
shown reflects only the COP/BDM connector order.
For a board with a COP (common on-chip processor) connector, which accesses the JTAG interface and which needs to reset
the JTAG module, simply wiring JTAG_TRST and PORRESET is not recommended.
Table 53. COP/BDM Interface Signals
BDM
Pin #
MPC5200B
I/O Pin
BDM
Connector
Internal
Pull Up/Down
External
Pull Up/Down
I/O1
1 With respect to the emulator tool’s perspective, Input is really an output from the embedded e300 core and
output is really an input to the core.
16
—
GND
—
15
TEST_SEL_0
ckstp_out
—
I
14
—
KEY
—
13
HRESET
hreset
—
10k Pull-Up
O
12
—
GND
—
11
SRESET
sreset
—
10k Pull-Up
O
10
—
N/C
—
9
JTAG_TMS
tms
100k Pull-Up
10k Pull-Up
O
8—
N/C
—
7
JTAG_TCK
tck
100k Pull-Up
10k Pull-Up
O
6—
VDD2
2 From the board under test, power sense for chip power.
——
—
5
—
halted3
3 HALTED is not available from e300 core.
——
I
4
JTAG_TRST
trst
100k Pull-Up
10k Pull-Up
O
3
JTAG_TDI
tdi
100k Pull-Up
10k Pull-Up
O
2
—
qack4
4 Input to the e300 core to enable/disable soft-stop condition during breakpoints. MPC5200B
internally ties CORE_QACK to GND in its normal/functional mode (always asserted).
——
O
1JTAG_TDO
tdo
—
I
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