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| 型號(hào)： | MPC5200VR400BR2 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 400 MHz, MICROPROCESSOR, PBGA272 |
| 封裝： | 27 X 27 MM, 1.27 MM PITCH, ROHS COMPLIANT, PLASTIC, BGA-272 |
| 文件頁(yè)數(shù)： | 17/72頁(yè) |
| 文件大?。?/td> | 978K |
| 代理商： | MPC5200VR400BR2 |
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MPC5200B Data Sheet, Rev. 4
24
Freescale Semiconductor
NOTES:
1. ACK can shorten the CS pulse width.
Wait States (WS) can be programmed in the Chip Select X Register, Bit field WaitP and WaitX. It can be specified from
0–65535.
2. In Large Flash and MOST Graphics mode the shared PCI/ATA pins, used as address lines, are released at the same moment
as the CS. This can cause the address to change before CS is deasserted.
3. ACK is input and can be used to shorten the CS pulse width.
4. Only available in Large Flash and MOST Graphics mode.
5. Only available in MOST Graphics mode.
6. Deadcycles are only used, if no arbitration to an other module (ATA or PCI) of the shared local bus happens. If arbitration
happens the bus can be driven within 4 IPB clocks by an other modules.
t10
DATA input setup before CS negation
8.5
—ns
—
A7.12
t11
DATA input hold after CS negation
0
(DC + 1) × tPCIck
ns
(6)
A7.13
t12
ACK assertion after CS assertion
tPCIck
—ns
(3)
A7.14
t13
ACK negation after CS negation
—tPCIck
ns
(3)
A7.15
t14
TS assertion before CS assertion
—6.9
ns
(4)
A7.16
t15
TS pulse width
tPCIck
ns
(4)
A7.17
t16
TSIZ valid before CS assertion
tIPBIck
—ns
(5)
A7.18
t17
TSIZ hold after CS negation
tIPBIck
—ns
(5)
A7.19
t18
ACK change before PCI clock
—2.0
ns
(1)
A7.20
t19
ACK change after PCI clock
—4.4
ns
(1)
A7.21
Table 24. Non-MUXed Mode Timing (continued)
Sym
Description
Min
Max
Units
Notes
SpecID
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