參數(shù)資料
型號: MPC5200VR400BR2
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 400 MHz, MICROPROCESSOR, PBGA272
封裝: 27 X 27 MM, 1.27 MM PITCH, ROHS COMPLIANT, PLASTIC, BGA-272
文件頁數(shù): 16/72頁
文件大?。?/td> 978K
代理商: MPC5200VR400BR2
MPC5200B Data Sheet, Rev. 4
Freescale Semiconductor
23
2. Minimum times are measured at the package pin with the load circuit, and maximum times are measured with the load circuit
as shown in the PCI Local Bus Specification.
3. REQ# and GNT# are point-to-point signals and have different input setup times than do bused signals. GNT# and REQ# have
a setup of 5 ns at 66 MHz. All other signals are bused.
4. See the timing measurement conditions in the PCI Local Bus Specification.
For Measurement and Test Conditions, see the PCI Local Bus Specification.
1.3.8
Local Plus Bus
The Local Plus Bus is the external bus interface of the MPC5200B. A maximum of eight configurable chip selects (CS) are
provided. There are two main modes of operation: non-MUXed (Legacy and Burst) and MUXED. The reference clock is the
PCI CLK. The maximum bus frequency is 66 MHz.
Definition of Acronyms and Terms:
WS = Wait State
DC = Dead Cycle
LB = Long Burst
DS = Data Size in Bytes
tPCIck = PCI clock period
tIPBIck = IPBI clock period
Figure 10. Timing Diagram—IPBI and PCI clock (example ratio: 4:1)
1.3.8.1
Non-MUXed Mode
Table 24. Non-MUXed Mode Timing
Sym
Description
Min
Max
Units
Notes
SpecID
tCSA
PCI CLK to CS assertion
4.6
10.6
ns
—A7.1
tCSN
PCI CLK to CS negation
2.9
7.0
ns
—A7.2
t1
CS pulse width
(2 + WS) × tPCIck
(2 +WS) ×tPCIck
ns
(1)
A7.3
t2
ADDR valid before CS assertion
tIPBIck
tPCIck
ns
—A7.4
t3
ADDR hold after CS negation
tIPBIck
—ns
(2)
A7.5
t4
OE assertion before CS assertion
—4.8
ns
—A7.6
t5
OE negation before CS negation
—2.7
ns
—A7.7
t6
RW valid before CS assertion
tPCIck
—ns
—A7.8
t7
RW hold after CS negation
tIPBIck
—ns
—A7.9
t8
DATA output valid before CS assertion
tIPBIck
—ns
A7.10
t9
DATA output hold after CS negation
tIPBIck
—ns
A7.11
PCI CLK
IPBI CLK
tIPBIck
tPCIck
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