參數(shù)資料
型號(hào)： MPC5200VR400BR2
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 400 MHz, MICROPROCESSOR, PBGA272
封裝： 27 X 27 MM, 1.27 MM PITCH, ROHS COMPLIANT, PLASTIC, BGA-272
文件頁數(shù)： 61/72頁
文件大?。?/td> 978K
代理商： MPC5200VR400BR2
MPC5200B Data Sheet, Rev. 4
64
Freescale Semiconductor
3
System Design Information
3.1
Power Up/Down Sequencing
Figure 51 shows situations in sequencing the I/O VDD (VDD_IO), Memory VDD (VDD_IO_MEM), PLL VDD
(PLL_AVDD), and Core VDD (VDD_CORE).
Figure 51. Supply Voltage Sequencing
VDD_MEM_IO
—
VDD_CORE
—
VSS_IO/CORE
—
SYS_PLL_AVDD
—
CORE_PLL_AVDD
—
1 All “open drain” outputs of the MPC5200B are actually regular three-state output drivers with the output data tied low
and the output enable controlled. Thus, unlike a true open drain, there is a current path from the external system to
the MPC5200B I/O power rail if the external signal is driven above the MPC5200B I/O power rail voltage.
Table 52. MPC5200B Pinout Listing (continued)
Name
Alias
Type
Power Supply
Output Driver
Type
Input
Type
Pull-up/
down
1.5 V
2.5 V
3.3 V
0
DC
P
o
w
e
rSupp
ly
V
o
ltage
VDD_IO,
VDD_IO_MEM (SDR)
VDD_IO_MEM (DDR)
VDD_CORE,
PLL_AVDD
Note: VDD_CORE should not exceed VDD_IO, VDD_IO_MEM or PLL_AVDD by more than 0.4 V at any time, including
power-up.
Note: It is recommended that VDD_CORE/PLL_AVDD should track VDD_IO/VDD_IO_MEM up to 0.9 V then separate
for completion of ramps.
Note: Input voltage must not be greater than the supply voltage (VDD_IO) VDD_IO_MEM, VDD_CORE, or PLL_AVDD)
by more than 0.5 V at any time, including during power-up.
Note: Use 1 microsecond or slower rise time for all supplies.
1
2
Time
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