參數(shù)資料
型號: MPC5200VR400BR2
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 400 MHz, MICROPROCESSOR, PBGA272
封裝: 27 X 27 MM, 1.27 MM PITCH, ROHS COMPLIANT, PLASTIC, BGA-272
文件頁數(shù): 11/72頁
文件大?。?/td> 978K
代理商: MPC5200VR400BR2
MPC5200B Data Sheet, Rev. 4
Freescale Semiconductor
19
Figure 6. Timing Diagram—Standard SDRAM Memory Write Timing
1.3.6.3
Memory Interface Timing-DDR SDRAM Read Command
The SDRAM Memory Controller uses a 1/4 period delayed MDQS strobe to capture the MDQ data. The 1/4 period delay value
is calculated automatically by hardware.
Table 20. DDR SDRAM Memory Read Timing
Sym
Description
Min
Max
Units
SpecID
tmem_clk
MEM_CLK period
7.5
ns
A5.15
tvalid
Control Signals, Address and MBA
valid after rising edge of MEM_CLK
—tmem_clk ×0.5 +0.4
ns
A5.16
thold
Control Signals, Address and MBA
hold after rising edge of MEM_CLK
tmem_clk × 0.5
ns
A5.17
datasetup
Setup time relative to MDQS
0.4
ns
A5.18
datahold
Hold time relative to MDQS
2.6
ns
A5.19
MEM_CLK
Control Signals
MDQ (Data)
MA (Address)
NOTE: Control Signals are composed of RAS, CAS, MEM_WE, MEM_CS, MEM_CS1 and CLK_EN
Active
NOP
WRITE
NOP
thold
Row
Column
MBA (Bank Selects)
datahold
datavalid
tvalid
thold
tvalid
thold
tvalid
DQM (Data Mask)
DMvalid
DMhold
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