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參數(shù)資料
| 型號： | MPC5200VR400BR2 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 400 MHz, MICROPROCESSOR, PBGA272 |
| 封裝： | 27 X 27 MM, 1.27 MM PITCH, ROHS COMPLIANT, PLASTIC, BGA-272 |
| 文件頁數(shù)： | 21/72頁 |
| 文件大小： | 978K |
| 代理商： | MPC5200VR400BR2 |
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MPC5200B Data Sheet, Rev. 4
28
Freescale Semiconductor
Figure 13. Timing Diagram—MUXed Mode
1.3.9
ATA
The MPC5200B ATA Controller is completely software programmable. It can be programmed to operate with ATA protocols
using their respective timing, as described in the ANSI ATA-4 specification. The ATA interface is completely asynchronous in
nature. Signal relationships are based on specific fixed timing in terms of timing units (nanoseconds).
ATA data setup and hold times, with respect to Read/Write strobes, are software programmable inside the ATA Controller. Data
setup and hold times are implemented using counters. The counters count the number of ATA clock cycles needed to meet the
ANSI ATA-4 timing specifications. For details, see the ANSI ATA-4 specification and how to program an ATA Controller and
ATA drive for different ATA protocols and their respective timing. See the MPC5200B User’s Manual (MPC5200BUM).
The MPC5200B ATA Host Controller design makes data available coincidentally with the active edge of the WRITE strobe in
PIO and Multiword DMA modes.
Write data is latched by the drive at the inactive edge of the WRITE strobe. This gives ample setup time beyond that
required by the ATA-4 specification.
Data is held unchanged until the next active edge of the WRITE strobe. This gives ample hold time beyond that
required by the ATA-4 specification.
PCI CLK
AD[24:0] (wr)
CSx
R/W
ALE
AD[30:28] (wr)
AD[26:25] (wr)
AD[31,27] (wr)
Address[7:31]
Bank[0:1] bits
TSIZ[0:2] bits
ACK
Data
Data tenure
Address tenure
TS
Data
AD[31:0] (rd)
Data
t4
t13
t5
t1
Address latch
t7
t6
t11
t9
t12
t10
t8
t2
t3
OE
t14
t15
t16
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