參數(shù)資料
型號(hào)： MCIMX514AJM6C
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PBGA529
封裝： 19 X 19 MM, 0.8 MM PITCH, ROHS COMPLIANT, BGA-529
文件頁數(shù)： 88/172頁
文件大小： 2218K
代理商： MCIMX514AJM6C
i.MX51A Automotive and Infotainment Applications Processors, Rev. 4
22
Freescale Semiconductor
Electrical Characteristics
4.2.1
Power-Up Sequence
Figure 2 shows the power-up sequence.
Figure 2. Power-Up Sequence
NOTE
The POR_B input must be immediately asserted at power-up and remain
asserted until after the last power rail is at its working voltage.
For more information on power up, see i.MX51 Power-Up Sequence
(AN4053)
4.3
I/O DC Parameters
This section includes the DC parameters of the following I/O types:
General Purpose I/O and High-Speed General Purpose I/O (GPIO/HSGPIO)
Double Data Rate 2 (DDR2)
Low Voltage I/O (LVIO)
Ultra High Voltage I/O (UHVIO)
High-Speed I2C and I2C
Enhanced Secure Digital Host Controller (eSDHC)
AHVDDRGB
NVCC_TV_BACK
TVDAC_DHVDD
VDD_DIG_PLL_A/B
VDD_ANA_PLL_A/B
NVCC_OSC
NVCC_USBPHY
VDDA33
NVCC_EMI_DRAM
NVCC_SRTC_POW
VDDA
NVCC_NANDF_x
NVCC_PER15
NVCC_PER17
NVCC_HS4_1
NVCC_HS4_2
NVCC_HS6
NVCC_HS10
NVCC_PERx2
NVCC_EMI
NVCC_IPU
NVCC_I2C
VDDGP4
VDD_FUSE1
VCC
1. VDD_FUSE should only be powered when writing.
2. NVCC_PERx refers to NVCC_PER 3, 5, 8, 9, 10, 11, 12, 13, 14.
3. No power-up sequence dependencies exist between the supplies shown in the block diagram shaded in gray.
4. There is no requirement for VDDGP to be preceded by any other power supply other than NVCC_SRTC_POW.
5. If all of the UHVIO supplies (NVCC_NANDFx, NVCC_PER15 and NVCC_PER17) are less than 2.75 V then there is no
requirement on the power up sequence order between NVCC_EMI_DRAM and the UHVIO supplies. However, if the voltage
is 2.75 V and above, then NVCC_EMI_DRAM needs to power up before the UHVIO supplies as shown here.
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