參數(shù)資料
型號: MCIMX514AJM6C
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: SPECIALTY MICROPROCESSOR CIRCUIT, PBGA529
封裝: 19 X 19 MM, 0.8 MM PITCH, ROHS COMPLIANT, BGA-529
文件頁數(shù): 132/172頁
文件大小: 2218K
代理商: MCIMX514AJM6C
i.MX51A Automotive and Infotainment Applications Processors, Rev. 4
62
Freescale Semiconductor
Electrical Characteristics
Figure 32 shows the timing diagram for mDDR SDRAM write cycle. The timing parameters for this
diagram is shown in Table 56.
Figure 32. mDDR SDRAM Write cycle Timing Diagram
Table 56. mDDR SDRAM Write Cycle Parameter Table1
1 Test conditions are: Capacitance 15 pF for DDR PADS. Recommended drive strengths is medium for SDCLK and high for
address and controls.
ID
Parameter
Symbol
200 MHz2
2 SDRAM CLK and DQS related parameters are being measured from the 50% point. that is, high is defined as 50% of signal
value and low is defined as 50% as signal value. DDR SDRAM CLK parameters are measured at the crossing point of SDCLK
and SDCLK (inverted clock).
166 MHz
133 MHz
Unit
Min
Max
Min
Max
Min
Max
DD17
DQ and DQM setup time to DQS
tDS3
3 This parameter is affected by pad timing. If the slew rate is < 1 V/ns, 0.1 ns should be increased to this value.
0.48
0.6
0.8
ns
DD18
DQ and DQM hold time to DQS
tDH1
0.48
0.6
0.8
ns
DD19
Write cycle DQS falling edge to
SDCLK output setup time
tDSS
0.2
0.2
0.2
tCK
DD20
Write cycle DQS falling edge to
SDCLK output hold time
tDSH
0.2
0.2
0.2
tCK
DD21
Write command to first DQS latching
transition
tDQSS
0.75
1.25
0.75
1.25
0.75
1.25
tCK
DD22
DQS high level width
tDQSH
0.4
0.6
0.4
0.6
0.4
0.6
tCK
DD23
DQS low level width
tDQSL
0.4
0.6
0.4
0.6
0.4
0.6
tCK
SDCLK
SDCLK_B
DQS (output)
DQ (output)
DQM (output)
Data
DM
DD17
DD18
DD19
DD20
DD21
DD23
DD22
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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