參數(shù)資料
型號： MCIMX514AJM6C
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PBGA529
封裝： 19 X 19 MM, 0.8 MM PITCH, ROHS COMPLIANT, BGA-529
文件頁數(shù)： 123/172頁
文件大?。?/td> 2218K
代理商： MCIMX514AJM6C
i.MX51A Automotive and Infotainment Applications Processors, Rev. 4
54
Freescale Semiconductor
Electrical Characteristics
WE5
Clock rise to address
invalid
0.5t-1.25
—
t-1.25
t+1.75
2t-1.25
2t+1.75
3t-1.25
3t+1.75
WE6
Clock rise to CSx_B valid
-0.5t-1.25
-0.5t+1.75
-t-1.25
-t+1.75
-t-1.25
-t+1.75
-t-1.25
-t+1.75
WE7
Clock rise to CSx_B
invalid
0.5t-1.25
0.5t+1.75
2t-1.25
2t+1.75
2t-1.25
2t+1.75
3t-1.25
3t+1.75
WE8
Clock rise to WE_B Valid
-0.5t-1.25
-0.5t+1.75
-t-1.25
-t+1.75
-t-1.25
-t+1.75
-t-1.25
-t+1.75
WE9
Clock rise to WE_B
Invalid
0.5t-1.25
0.5t+1.75
2t-1.25
2t+1.75
2t-1.25
2t+1.75
3t-1.25
3t+1.75
WE10
Clock rise to OE_B Valid
-0.5t-1.25
-0.5t+1.75
-t-1.25
-t+1.75
-t-1.25
-t+1.75
-t-1.25
-t+1.75
WE11
Clock rise to OE_B
Invalid
0.5t-1.25
0.5t+1.75
2t-1.25
2t+1.75
2t-1.25
2t+1.75
3t-1.25
3t+1.75
WE12
Clock rise to BEy_B Valid
-0.5t-1.25
-0.5t+1.75
-t-1.25
-t+1.75
-t-1.25
-t+1.75
-t-1.25
-t+1.75
WE13
Clock rise to BEy_B
Invalid
0.5t-1.25
0.5t+1.75
t-1.25
t+1.75
2t-1.25
2t+1.75
3t-1.25
3t+1.75
WE14
Clock rise to ADV_B
Valid
-0.5t-1.25
-0.5t+1.75
-t-1.25
-t+1.75
-t-1.25
-t+1.75
-t-1.25
-t+1.75
WE15
Clock rise to ADV_B
Invalid
0.5t-1.25
0.5t+1.75
t-1.25
t+1.75
2t-1.25
2t+1.75
3t-1.25
3t+1.75
WE164 Clock rise to Output Data
Valid
-0.5t-1.25
-0.5t+1.75
-t-1.25
-t+1.75
-t-1.25
-t+1.75
-t-1.25
-t+1.75
WE174 Clock rise to Output Data
Invalid
0.5t-1.25
0.5t+1.75
t-1.25
t+1.75
2t-1.25
2t+1.75
3t-1.25
3t+1.75
WE184 Input Data setup time to
Clock rise
2
—
4
—
———
—
WE194 Input Data hold time from
Clock rise
2
—
2
—
———
—
WE20
WAIT_B setup time to
Clock rise
2
—
4
—
———
—
WE21
WAIT_B hold time from
Clock rise
2
—
2
—
———
—
1 t is axi_clk cycle time. The maximum allowed axi_clk frequency is 133 MHz, whereas the maximum allowed BCLK frequency
is 104 MHz. As a result if BCD = 0, axi_clk must be
≤104 MHz. If BCD = 1, then 133 MHz is allowed for axi_clk, resulting in a
BCLK of 66.5 MHz. When the clock branch to WEIM is decreased to 104 MHz, other busses are impacted which are clocked
from this source. See the CCM chapter of the i.MX51 Multimedia Applications Processor Reference Manual (MCIMX51RM)
for a detailed clock tree description.
2 BCLK parameters are being measured from the 50% point that is, high is defined as 50% of signal value and low is defined
as 50% as signal value.
3 For signal measurements “High” is defined as 80% of signal value and “Low” is defined as 20% of signal value.
4 The lower 16 bits of the WEIM bus are limited to 90 MHz.”
Table 53. WEIM Bus Timing Parameters (continued)1
ID
Parameter
BCD = 0
BCD = 1
BCD = 2
BCD = 3
Min
Max
Min
Max
Min
Max
Min
Max
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MCIMX514AJM6CR2 制造商:Freescale Semiconductor 功能描述:ELVIS 3.0 AUTO - Tape and Reel
MCIMX515CJM6C 功能描述:處理器 - 專門應(yīng)用 iMX515 App Processor RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432
MCIMX515CJM6CR2 功能描述:處理器 - 專門應(yīng)用 i.MX51 32bit 800 MHz RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432
MCIMX515DJM8C 功能描述:處理器 - 專門應(yīng)用 iMX515 App Processor Extended Temp RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432
MCIMX515DJM8C 制造商:Freescale Semiconductor 功能描述:; LEADED PROCESS COMPATIBLE:YES; PEAK RE
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