參數(shù)資料
型號： MCIMX514AJM6C
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PBGA529
封裝： 19 X 19 MM, 0.8 MM PITCH, ROHS COMPLIANT, BGA-529
文件頁數(shù)： 158/172頁
文件大小： 2218K
代理商： MCIMX514AJM6C
i.MX51A Automotive and Infotainment Applications Processors, Rev. 4
86
Freescale Semiconductor
Electrical Characteristics
4.7.8.4
IPU Display Interface Timing
The IPU Display Interface supports two kinds of display’s accesses: synchronous and asynchronous. There
are two groups of external interface pins to provide synchronous and asynchronous controls accordantly.
4.7.8.4.1
Synchronous Controls
The synchronous control is a signal that changes its value as a function either of a system or of an external
clock. This control has a permanent period and a permanent wave form.
There are special physical outputs to provide synchronous controls:
The ipp_disp_clk is a dedicated base synchronous signal that is used to generate a base display
(component, pixel) clock for a display.
The ipp_pin_1– ipp_pin_7 are general purpose synchronous pins, that can be used to provide
HSYNC, VSYNC, DRDY or any else independent signal to a display.
The IPU has a system of internal binding counters for internal events (like HSYNC/VSYCN and so on)
calculation. The internal event (local start point) is synchronized with internal DI_CLK. A suitable control
starts from the local start point with predefined UP and DOWN values to calculate control’s changing
points with half DI_CLK resolution. A full description of the counters system is in the IPU chapter of the
i.MX51 Multimedia Applications Processor Reference Manual (MCIMX51RM).
4.7.8.4.2
Asynchronous Controls
The asynchronous control is a data oriented signal that changes its a value with an output data according
to an additional internal flags coming with the data.
There are special physical outputs to provide asynchronous controls, as follows:
The ipp_d0_cs and ipp_d1_cspins are dedicated to provide chip select signals to two displays
The ipp_pin_11– ipp_pin_17 are general purpose asynchronous pins, that can be used to provide
WR. RD, RS or any else data oriented signal to display.
NOTE
The IPU has independent signal generators for asynchronous signals
toggling. When a DI decides to put a new asynchronous data in the bus, a
new internal start (local start point) is generated. The signals generators
calculate predefined UP and DOWN values to change pins states with half
DI_CLK resolution.
4.7.8.5
Synchronous Interfaces to Standard Active Matrix TFT LCD Panels
4.7.8.5.1
IPU Display Operating Signals
The IPU uses four control signals and data to operate a standard synchronous interface:
IPP_DISP_CLK—Clock to display
HSYNC—Horizontal synchronization
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MCIMX514AJM6CR2 制造商:Freescale Semiconductor 功能描述:ELVIS 3.0 AUTO - Tape and Reel
MCIMX515CJM6C 功能描述:處理器 - 專門應(yīng)用 iMX515 App Processor RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432
MCIMX515CJM6CR2 功能描述:處理器 - 專門應(yīng)用 i.MX51 32bit 800 MHz RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432
MCIMX515DJM8C 功能描述:處理器 - 專門應(yīng)用 iMX515 App Processor Extended Temp RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432
MCIMX515DJM8C 制造商:Freescale Semiconductor 功能描述:; LEADED PROCESS COMPATIBLE:YES; PEAK RE
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