參數(shù)資料
型號: MCIMX27
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: Multimedia Applications Processor(多媒體應(yīng)用處理器)
中文描述: 多媒體應(yīng)用處理器(多媒體應(yīng)用處理器)
文件頁數(shù): 92/118頁
文件大小: 1159K
代理商: MCIMX27
i.MX27 Data Sheet, Advance Information, Rev. 0.1
92
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Signal Descriptions
NOTE
High is defined as 80% of signal value and low is defined as 20% of signal
value.
Test conditions: pad voltage, 1.7V-1.95 V; pad capacitance, 25 pF.
Recommended drive strength for all controls, address, and BCLK is Max
High.
WE4
Clock rise/fall to CS[x] invalid
0.45
2.25
ns
WE5
Clock rise/fall to RW Valid
0.90
2.60
ns
WE6
Clock rise/fall to RW Invalid
0.90
2.60
ns
WE7
Clock rise/fall to OE Valid
1.17
3.57
ns
WE8
Clock rise/fall to OE Invalid
1.17
3.57
ns
WE9
Clock rise/fall to EB[x] Valid
0.73
2.43
ns
WE10
Clock rise/fall to EB[x] Invalid
0.73
2.43
ns
WE11
Clock rise/fall to LBA Valid
1.03
2.84
ns
WE12
Clock rise/fall to LBA Invalid
1.03
2.84
ns
WE13
Clock rise/fall to Output Data Valid
1.04
4.01
ns
WE14
Clock rise to Output Data Invalid
1.04
4.01
ns
WE15
Input Data Valid to Clock rise, FCE=0
6.95
ns
WE16
Cloc/k rise to Input Data Invalid, FCE=0
2.35
ns
WE17
Input Data Valid to Clock rise, FCE=1
1.24
ns
WE18
Clock rise to Input Data Invalid, FCE=1
0.23
ns
WE19
ECB setup time, FCE=0
7.23
ns
WE20
ECB hold time, FCE=0
2.93
ns
WE21
ECB setup time, FCE=1
1.08
ns
WE22
ECB hold time, FCE=1
0
ns
WE23
DTACK setup time
5.35
ns
WE24
DTACK hold time
3.19
ns
WE25
BCLK High Level Width
1
3.0
ns
WE26
BCLK Low Level Width
1
3.0
ns
WE27
BCLK Cycle time
1
7.5
ns
1
BCLK parameters are being measured from the 50% point—that is, high is defined as 50% of signal
value and low is defined as 50% of signal value.
Table 49. WEIM Bus Timing Parameters (continued)
ID
Parameter
1.8 V
Unit
Min
Max
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