參數(shù)資料
型號: MCIMX27
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: Multimedia Applications Processor(多媒體應(yīng)用處理器)
中文描述: 多媒體應(yīng)用處理器(多媒體應(yīng)用處理器)
文件頁數(shù): 49/118頁
文件大?。?/td> 1159K
代理商: MCIMX27
Signal Descriptions
i.MX27 Data Sheet, Advance Information, Rev. 0.1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
49
Figure 6
depicts Write 1 Sequence timing,
Figure 7
depicts the Read Sequence timing, and
Table 18
lists
the timing parameters.
Figure 6. Write 1 Sequence Timing Diagram
Figure 7. Read Sequence Timing Diagram
3.5.3
ATA Electrical Specifications
This section describes the electrical information of the Parallel ATA module compliant with ATA/ATAPI-6
specification.
Parallel ATA module can work on PIO/Multi-Word DMA/Ultra DMA transfer modes. Each transfer mode
has different data transfer rate, Ultra DMA mode 4 data transfer rate is up to 100 MB/s. Parallel ATA
module interface consist of a total of 29 pins, Some pins act on different function in different transfer
mode. There are different requirements of timing relationships among the function pins conform with
ATA/ATAPI-6 specification and these requirements are configurable by the ATA module registers.
Below defines the AC characteristics of all the interface signals on all data transfer modes.
Table 17. WR0 Sequence Timing Parameters
ID
Parameter
Symbol
Min
Typ
Max
Units
OW5
Write 0 Low Time
t
WR0_low
60
100
120
μs
OW6
Transmission Time Slot
t
SLOT
OW5
117
120
μs
Table 18. Write 1/Read Timing Parameters
ID
Parameter
Symbol
Min
Typ
Max
Units
OW7
Write 1/Read Low Time
t
LOW1
1
5
15
μs
OW8
Transmission Time Slot
t
SLOT
60
117
120
μs
OW9
Release Time
t
RELEASE
15
45
μs
OW7
OW8
One-Wire bus
(BATT_LINE)
OW7
OW8
OW9
One-Wire bus
(BATT_LINE)
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