參數(shù)資料
型號: MCIMX27
廠商: 飛思卡爾半導體(中國)有限公司
英文描述: Multimedia Applications Processor(多媒體應(yīng)用處理器)
中文描述: 多媒體應(yīng)用處理器(多媒體應(yīng)用處理器)
文件頁數(shù): 66/118頁
文件大?。?/td> 1159K
代理商: MCIMX27
i.MX27 Data Sheet, Advance Information, Rev. 0.1
66
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Signal Descriptions
3.5.13
NAND Flash Controller Interface (NFC)
Figure 30
,
Figure 31
,
Figure 32
, and
Figure 33
show the relative timing requirements among different
signals of the NFC at module level, and
Table 34
lists the timing parameters. The NAND Flash Controller
(NFC) timing parameters are based on the internal NFC clock generated by the Clock Controller module,
where time T is the period of the NFC clock in ns. The relationship between the NFC clock and the external
timing parameters of the NFC is provided in
Table 34
.
Table 34
also provides two examples of external timing parameters with NFC clock frequencies of
22.17 MHz and 33.25 MHz. Assuming a 266 MHz FCLK (CPU clock), NFCDIV should be set to
divide-by-12 to generate a 22.17 MHz NFC clock and divide-by-8 to generate a 33.25 MHz NFC clock.
The user should compare the parameters of the selected NAND Flash memory with the NFC external
timing parameters to determine the proper NFC clock. The maximum NFC clock allowed is 66 MHz. It
should also be noted that the default NFC clock on power up is 16.63 MHz.
Figure 30. Command Latch Cycle Timing Diagram
MSHC_DATA
Setup time
tDsu
8
ns
Hold time
tDh
1
ns
Output delay time
tDd
15
ns
Table 33. Parallel Interface Timing Parameters (continued)
Signal
Parameter
Symbol
Standards
Unit
Min
Max
NFCLE
NFCE
NFWE
NFALE
NFIO[7:0]
command
NF9
NF8
NF1
NF2
NF5
NF3
NF4
NF6
NF7
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