參數(shù)資料
型號: MCIMX27
廠商: 飛思卡爾半導體(中國)有限公司
英文描述: Multimedia Applications Processor(多媒體應(yīng)用處理器)
中文描述: 多媒體應(yīng)用處理器(多媒體應(yīng)用處理器)
文件頁數(shù): 89/118頁
文件大小: 1159K
代理商: MCIMX27
Signal Descriptions
i.MX27 Data Sheet, Advance Information, Rev. 0.1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
89
Figure 51. SSI Receiver with External Clock Timing Diagram
NOTE
All the timings for the SSI are given for a non-inverted serial clock polarity
(TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the
polarity of the clock and/or the frame sync have been inverted, all the timing
remains valid by inverting the clock signal STCK/SRCK and/or the frame
sync STFS/SRFS shown in the tables and in the figures.
Table 48. SSI Receiver with External Clock Timing Parameters
ID
Parameter
Min
Max
Unit
External Clock Operation
SS22
(Tx/Rx) CK clock period
81.4
ns
SS23
(Tx/Rx) CK clock high period
36.0
ns
SS24
(Tx/Rx) CK clock rise time
6.0
ns
SS25
(Tx/Rx) CK clock low period
36.0
ns
SS26
(Tx/Rx) CK clock fall time
6.0
ns
SS28
(Rx) CK high to FS (bl) high
–10.0
15.0
ns
SS30
(Rx) CK high to FS (bl) low
10.0
ns
SS32
(Rx) CK high to FS (wl) high
–10.0
15.0
ns
SS34
(Rx) CK high to FS (wl) low
10.0
ns
SS35
(Tx/Rx) External FS rise time
6.0
ns
SS36
(Tx/Rx) External FS fall time
6.0
ns
SS40
SRXD setup time before (Rx) CK low
10.0
ns
SS41
SRXD hold time after (Rx) CK low
2.0
ns
SS24
SS34
SS35
SS30
SS28
SS26
SS25
SS23
DAM1_T_CLK
(Input)
DAM1_T_FS (bl)
(Input)
DAM1_T_FS (wl)
(Input)
DAM1_RXD
(Input)
SS40
SS22
SS32
SS36
SS41
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