參數(shù)資料
型號: MCIMX27
廠商: 飛思卡爾半導體(中國)有限公司
英文描述: Multimedia Applications Processor(多媒體應(yīng)用處理器)
中文描述: 多媒體應(yīng)用處理器(多媒體應(yīng)用處理器)
文件頁數(shù): 78/118頁
文件大?。?/td> 1159K
代理商: MCIMX27
i.MX27 Data Sheet, Advance Information, Rev. 0.1
78
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Signal Descriptions
Figure 41. Mobile DDR SDRAM DQ versus DQS and SDCLK Read Cycle Timing Diagram
NOTE
SDRAM CLK and DQS related parameters are being measured from the
50% point—that is, high is defined as 50% of signal value and low is
defined as 50% of signal value.
The timing parameters are similar to the ones used in SDRAM data
sheets—that is,
Table 41
indicates SDRAM requirements. All output signals
are driven by the ESDCTL at the negative edge of SDCLK and the
parameters are measured at maximum memory frequency.
3.5.15.1
SDHC Electrical DC Characteristics
Table 42
lists the SDHC electrical DC characteristics.
Table 41. Mobile DDR SDRAM Read Cycle Timing Parameters
ID
Parameter
Symbol
Min
Max
Unit
SD21 DQS–DQ Skew (defines the Data valid window in read cycles related to DQS).
tDQSQ
0.85
ns
SD22 DQS DQ HOLD time from DQS
tQH
2.3
ns
SD23 DQS output access time from SDCLK posedge
tDQSCK
6.7
ns
Table 42. SDHC Electrical DC Characteristics
ID
Parameter
Min
Max
Unit
Comments
General
SD10
Peak Voltage on All Lines
–0.3
V
DD
+ 0.3
V
All Inputs
SD11
Input Leakage Current
–10
10
μ
A
All Outputs
SD12
Output Leakage Current
–10
10
μ
A
Power Supply
SDCLK
SDCLK
DQS (input)
DQ (input)
Data
Data
Data
Data
Data
Data
Data
Data
SD23
SD21
SD22
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