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Chip Select Module
MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3
8-4
Freescale Semiconductor
Table 8-3 describes the interaction between CSBRn[EBI], OE/RD, R/W, and SDWE.
NOTE
The MCF5272 compares the address for the current bus transfer with the
address and mask bits in the CSBRs and CSORs looking for a match. The
priority is listed in
Table 8-4 (from highest priority to lowest priority):
4–2
TM
Transfer modifier. Operates with TT to determine the access type.
TT
TM
Function
0x
000
Reserved
0x
001
User data access
0x
010
User instruction access
0x
011–100
Reserved
0x
101
Supervisor data access
0x
110
Supervisor instruction access
0x
111
Reserved
10
000–100
Reserved
10
101
Emulator mode data access
10
110
Emulator mode instruction access
10
111
Reserved
11
000
CPU space access
11
001
Interrupt acknowledge level 1
11
010
Interrupt acknowledge level 2
11
011
Interrupt acknowledge level 3
11
100
Interrupt acknowledge level 4
11
101
Interrupt acknowledge level 5
11
110
Interrupt acknowledge level 6
11
111
Interrupt acknowledge level 7
1
CTM
Compare TM. Enables comparison between the access type and the TM and TT bits.
0 TT and TM register bits do not affect address match.
1 TT and TM register bits must match the access type for an address match to occur.
0
ENABLE
Enable. Disables/enables the chip select. When disabled, the chip select is never asserted, regardless of
the address on the internal bus. ENABLE is 0 at reset, except CS0 which is 1.
0 Chip select is disabled, no matches can occur and chip select output cannot assert.
1 Chip select is enabled, bus cycles are compared against register contents.
Table 8-3. Output Read/Write Strobe Levels versus Chip Select EBI Code
EBI
EBI Function
Access Type
OE/RD
R/W
SDWE
00
SRAM, ROM
Write
High
Low
High
Read
Low
High
01
SDRAM
Write
High
Low
Read
High
11
SRAM, ROM
Write
High
Low
High
Read
Low
High
Table 8-2. CSBRn Field Descriptions (continued)
Bits
Name
Description