![](http://datasheet.mmic.net.cn/Freescale-Semiconductor/MCF5272VF66J_datasheet_98909/MCF5272VF66J_420.png)
Signal Descriptions
MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3
19-10
Freescale Semiconductor
TRST
DSCLK
—
JTAG reset/BDM clock
D4
I
USB_CLK
—
USB external 48-MHz
clock input
J1
I
USB_D+
—
USB line driver high,
analog5
F1
O
–
30
USB_D–
—
USB line driver low,
F2
O
–
30
USB_GND
—
USB transceiver GND
G2
I
USB_VDD
—
USB transceiver VDD
G1
I
VDD
+3.3V
—
F[5,6]
F[9,10]
G[5,10]
H[5,10]
J[5,6]
J[9,10]
K[7,8]
N13
1 No entry in this column means that after reset the pin is not reconfigurable and has only one definition.
2 WSEL, BUSW1, BUSW0, HIZ, and others, refers to function determined by pull-up or pull-down value as seen by these
address pins during reset.
3 “Port x Cntl Reg” refers to pin function programmed by software writing to GPIO port configuration registers.
4 MTMOD means that pin function is determined by state of the MTMOD signal.
5 Requires external protection circuitry to meet USB 1.1 electrical requirements under all conditions (see 12.5.3, Table 19-1. Signal Descriptions Sorted by Function (Sheet 8 of 8)
Configured
by
(see notes)1
Pin Functions
Description
Map
BGA
Pin
I/O
Drive
(mA)
Cpf
0 (Reset)
1
2
3