![](http://datasheet.mmic.net.cn/Freescale-Semiconductor/MCF5272VF66J_datasheet_98909/MCF5272VF66J_343.png)
Queued Serial Peripheral Interface (QSPI) Module
MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor
14-5
A write to QDR causes data to be written to the RAM entry specified by QAR[ADDR] and causes the
value in QAR to increment. Correspondingly, a read at QDR returns the data in the RAM at the address
specified by QAR[ADDR]. This also causes QAR to increment. A read access requires a single wait state.
14.4.1.1
Receive RAM
Data received by the QSPI is stored in the receive RAM segment located at 0x10 to 0x1F in the QSPI RAM
space. The user reads this segment to retrieve data from the QSPI. Data words with less than 16 bits are
stored in the least significant bits of the RAM. Unused bits in a receive queue entry are set to zero upon
completion of the individual queue entry.
NOTE
Throughout ColdFire documentation, ‘word’ is used consistently and
exclusively to designate a 16-bit data unit. The only exceptions to this
appear in discussions of serial communication modules such as QSPI that
support variable-length data units. To simplify these discussions the
functional unit is referred to as a ‘word’ regardless of length.
QWR[CPTQP] shows which queue entries have been executed. The user can query this field to determine
which locations in receive RAM contain valid data.
Relative
Address
Register
Function
0x00
QTR0
Transmit RAM
0x01
QTR1
.
16 bits wide
..
0x0F
QTR15
0x10
QRR0
Receive RAM
0x11
QRR1
.
16 bits wide
..
0x1F
QRR15
0x20
QCR0
Command RAM
0x21
QCR1
.
8 bits wide
..
0x2F
QCR15
Figure 14-2. QSPI RAM Model