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Physical Layer Interface Controller (PLIC)
MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor
13-37
13.6.2.2
Interrupt Configuration Example
The PnICR registers should be configured according to the specific interrupts, periodic and aperiodic,
required for each port. In addition, the port interrupt enable, (PnICR[IE]) should be set for each active port
prior to receiving interrupts.
Assuming port 1 is configured as in the above example then the following configuration would enable
periodic interrupts on port 1 with only the D channel active.
Figure 13-36. Port 1 Interrupt Configuration Register (P1ICR)
The programming of the P1ICR in the above example is achieved with the following ColdFire code
sequence assuming the equates and init sections as in the previous P1CR example:
...
move.w
#0x8024,d0
; port 1 IE and D-channel interrupts enabled
move.w
d0,P1ICR(A5)
; write value to PnICR
...
GCI only
Port 0 only
IE enabled
Reserved
DTIE enabled
B2TIE disabled
DRIE enabled
B2RIE disabled
15 14 13 12 11 10
98765
43210
P1ICR
1
0
000000001
00100
0x
80
24
B1RIE disabled
B1TIE disabled