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System Integration Module (SIM)
MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3
6-10
Freescale Semiconductor
6.2.6
Activate Low-Power Register (ALPR)
ALPR,
Figure 6-6, is used to put the MCF5272 into a low power mode (sleep or stop). A low-power mode
is activated by a write access with any data to ALPR followed by a STOP instruction.
The sequence to enter sleep mode is as follows:
1. Set power down and wakeup enable bits in the PMR as desired; set PMR[SLPEN].
2. Set the CPU interrupt priority level in the status register (SR). Interrupts below this level do not
reactivate the CPU. Note that any interrupt will cause the processor to exit low-power mode, but
only unmasked interrupts will cause the processor to resume operation.
3. Perform a write access with any data to ALPR.
4. Execute the STOP instruction. This must be the next instruction executed after the write to the
ALPR.
Sleep mode is exited by an interrupt request from by either an external device or an on-chip peripheral as
The sequence to enter stop mode is:
1. Set PMR[MOS]; clear PMR[SLPEN].
2. Set the CPU interrupt priority level in the status register (SR). Interrupts below this level do not
reactivate the CPU.
3. Perform a write access with any data to ALPR.
4. Execute the STOP instruction. This must be the next instruction executed after the write to the
ALPR.
Stop mode is exited by an interrupt request from an external device as detailed in
Table 6-7.15
0
Field
ALPHR
Reset
0000_0000_0000_0000
R/W
Write only
Address
MBAR + 0x00E
Figure 6-6. Activate Low-Power Register (ALPR)
Table 6-7. Exiting Sleep and Stop Modes
Interrupt Source
Exit Sleep
Exit Stop USB Wake-on-Ring
Interrupts, INT6–INT2
Yes
No
Interrupt, INT1
Yes
USART1, USART2
Yes, interrupt and Rx signal change
No
QSPI
Yes
No
USB
Yes, interrupt and Rx signal change
No
PLIC
Yes, interrupt
No
General purpose I/O
No