MCF5272 ColdFire Integrated Microprocessor User鈥檚 Manual, Rev. 3 Freescale Semic" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� MCF5272VF66R2
寤犲晢锛� Freescale Semiconductor
鏂囦欢闋佹暩(sh霉)锛� 511/544闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC MCU 32BIT 66MHZ 196-MAPBGA
妯欐簴鍖呰锛� 750
绯诲垪锛� MCF527x
鏍稿績铏曠悊鍣細 Coldfire V2
鑺珨灏哄锛� 32-浣�
閫熷害锛� 66MHz
閫i€氭€э細 EBI/EMI锛屼互澶恫(w菐ng)锛孖²C锛孲PI锛孶ART/USART锛孶SB
澶栧湇瑷�(sh猫)鍌欙細 DMA锛學DT
杓稿叆/杓稿嚭鏁�(sh霉)锛� 32
绋嬪簭瀛樺劜鍣ㄥ閲忥細 16KB锛�4K x 32锛�
绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 ROM
RAM 瀹归噺锛� 1K x 32
闆诲 - 闆绘簮 (Vcc/Vdd)锛� 3 V ~ 3.6 V
鎸暕鍣ㄥ瀷锛� 澶栭儴
宸ヤ綔婧害锛� 0°C ~ 70°C
灏佽/澶栨锛� 196-LBGA
鍖呰锛� 甯跺嵎 (TR)
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MCF5272 ColdFire Integrated Microprocessor User鈥檚 Manual, Rev. 3
Freescale Semiconductor
2-1
Chapter 2
ColdFire Core
This chapter provides an overview of the microprocessor core of the MCF5272. The chapter describes the
V2 programming model as it is implemented on the MCF5272. It also includes a full description of
exception handling, data formats, an instruction set summary, and a table of instruction timings.
2.1
Features and Enhancements
The MCF5272 is the most highly-integrated V2 standard product, containing a variety of communications
and general-purpose peripherals. The V2 core was designed to maximize code density and performance
while minimizing die area.
The following list summarizes MCF5272 features:
Variable-length RISC Version 2 microprocessor core
Two independent, decoupled pipelines鈥攖wo-stage instruction fetch pipeline (IFP) and two-stage
operand execution pipeline (OEP)
Three longword FIFO buffer provides decoupling between the pipelines
32-bit internal address bus supporting 4 Gbytes of linear address space
32-bit data bus
16 user-accessible, 32-bit-wide, general-purpose registers
Supervisor/user modes for system protection
Vector base register to relocate exception-vector table
Optimized for high-level language constructs
2.1.1
Decoupled Pipelines
The IFP prefetches instructions. The OEP decodes instructions, fetches required operands, then executes
the specified function. The two independent, decoupled pipeline structures maximize performance while
minimizing core size. Pipeline stages are shown in Figure 2-1 and are summarized as follows:
Two-stage IFP (plus optional instruction buffer stage)
鈥� Instruction address generation (IAG) calculates the next prefetch address.
鈥� Instruction fetch cycle (IC) initiates prefetch on the processor鈥檚 local instruction bus.
鈥� Instruction buffer (IB) optional stage uses FIFO queue to minimize effects of fetch latency.
Two-stage OEP
鈥� Decode, select/operand fetch (DSOC) decodes the instruction and selects the required
components for the effective address calculation, or the operand fetch cycle.
鈥� Address generation/execute (AGEX) calculates the operand address, or performs the execution
of the instruction.
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
MCF5272VM66R2 IC MCU 32BIT 66MHZ 196-MAPBGA
VI-21F-CU-S CONVERTER MOD DC/DC 72V 200W
VI-21D-CU-S CONVERTER MOD DC/DC 85V 200W
VI-21B-CU-S CONVERTER MOD DC/DC 95V 200W
VI-214-CU-S CONVERTER MOD DC/DC 48V 200W
鐩搁棞(gu膩n)浠g悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
MCF5272VF66R2J 鍔熻兘鎻忚堪:32浣嶅井鎺у埗鍣� - MCU V2CORE 4KSRAM RoHS:鍚� 鍒堕€犲晢:Texas Instruments 鏍稿績:C28x 铏曠悊鍣ㄧ郴鍒�:TMS320F28x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪閻橀牷鐜�:90 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:64 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:26 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:2.97 V to 3.63 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:LQFP-80 瀹夎棰ㄦ牸:SMD/SMT
MCF5272VM66 鍔熻兘鎻忚堪:寰檿鐞嗗櫒 - MPU 66MHz 63MIPS RoHS:鍚� 鍒堕€犲晢:Atmel 铏曠悊鍣ㄧ郴鍒�:SAMA5D31 鏍稿績:ARM Cortex A5 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪閻橀牷鐜�:536 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:32 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:128 KB 鎺ュ彛椤炲瀷:CAN, Ethernet, LIN, SPI,TWI, UART, USB 宸ヤ綔闆绘簮闆诲:1.8 V to 3.3 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:FBGA-324
MCF5272VM66 K75N 鍒堕€犲晢:FREESCALE-SEMI 鍔熻兘鎻忚堪:
MCF5272VM66J 鍔熻兘鎻忚堪:32浣嶅井鎺у埗鍣� - MCU V2CORE 4KSRAM RoHS:鍚� 鍒堕€犲晢:Texas Instruments 鏍稿績:C28x 铏曠悊鍣ㄧ郴鍒�:TMS320F28x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪閻橀牷鐜�:90 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:64 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:26 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:2.97 V to 3.63 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:LQFP-80 瀹夎棰ㄦ牸:SMD/SMT
MCF5272VM66J 鍒堕€犲晢:Freescale Semiconductor 鍔熻兘鎻忚堪:IC 32BIT MPU 66MHZ BGA-196