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Electrical Characteristics
MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor
23-17
23.6
Fast Ethernet AC Timing Specifications
MII signals use TTL signal levels compatible with devices operating at either 5.0 V or 3.3 V.
23.6.1
MII Receive Signal Timing (E_RxD[3:0], E_RxDV, E_RxER, and
E_RxCLK)
The receiver functions correctly up to a E_RxCLK maximum frequency of 25 MHz +1%. There is no
minimum frequency requirement. In addition, the processor clock frequency must exceed twice the
E_RxCLK frequency.
Figure 23-11. MII Receive Signal Timing Diagram
Table 23-11. MII Receive Signal Timing
Num
Characteristic 1
1 E_RxDV, E_RxCLK, and E_RxD0 have same timing in 10 Mbit 7-wire interface mode.
Min
Max
Unit
M1
E_RxD[3:0], E_RxDV, Rx_ERR to E_RxCLK setup
5
—
nS
M2
E_RxCLK to E_RxD[3:0], E_RxDV, Rx_ERR hold
5
—
nS
M3
E_RxCLK pulse-width high
35%
65%
E_RxCLK period
M4
E_RxCLK pulse-width low
35%
65%
E_RxCLK period
M1
M2
E_RxCLK (input)
E_RxD[3:0] (inputs)
E_RxDV
E_RxER
M3
M4