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Physical Layer Interface Controller (PLIC)
MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor
13-29
13.5.17 GCI C/I Channel Transmit Registers (P0GCIT–P3GCIT)
All bits in these registers are read/write and are cleared on hardware or software reset.
The PnGCIT registers are 8-bit registers containing the monitor channel bits to be transmitted for each of
the four ports on the MCF5272.
31
29
28
27
26
25
24
23
21
20
19
18
17
16
Field
—
R
C3C2C1
C0
—
R
C3
C2C1
C0
Chan
P0GCIT
P1GCIT
Reset
0000_0000_0000_0000
R/W
Read/Write
15
13
12
11
10
9
8
7
5
4
3
2
1
0
Field
—
R
C3C2C1
C0
—
R
C3
C2C1
C0
Chan
P2GCIT
P3GCIT
Reset
0000_0000_0000_0000
R/W
Read/Write
Addr
MBAR + 0x378 (P0GCIT), 0x379 (P1GCIT), 0x37A (P3GCIT), 0x37B (P4GCIT)
Figure 13-29. GCI C/I Channel Transmit Registers (P0GCIT–P3GCIT)
Table 13-12. P0GCIT–P3GCIT Field Descriptions
Bits
Name
Description
31–29, 23–21,
15–13, 7–5
—
Reserved, should be cleared.
28, 20, 12, 4
R
Ready. This bit is set, by the CPU to indicate to the C/I channel controller that data is ready for
transmission. The transition of this bit from a 0 to a 1 starts the C/I state machine which responds
with the ACK bit once transmission of two successive C/I words is complete. This bit is
automatically cleared by the GCI controller when it generates a transmit acknowledge (ACK bit in
PGCITSR register). The clearing of this bit by reading this register also clears the aperiodic GCT
interrupt.
27–24, 19–16,
11–8, 3–0
C3–C0
C/I bits. The CPU writes C/I data to be transmitted, on the GCI or SCIT channel 0, into these
positions. The CPU must ensure that this data is not overwritten before it has been transmitted the
required minimum amount of times, that is, so any change is detected and confirmed by a receiver.
A maskable interrupt is generated when this data has been successfully transmitted