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Queued Serial Peripheral Interface (QSPI) Module
MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor
14-9
14.5
Programming Model
The programming model for the QSPI consists of six registers. They are the QSPI mode register (QMR),
QSPI delay register (QDLYR), QSPI wrap register (QWR), QSPI interrupt register (QIR), QSPI address
register (QAR), and the QSPI data register (QDR).
There are a total of 80 bytes of memory used for transmit, receive, and control data. This memory is
accessed indirectly using QAR and QDR.
Registers and RAM are written and read by the CPU.
14.5.1
QSPI Mode Register (QMR)
The QMR register, shown in
Figure 14-3, determines the basic operating modes of the QSPI module.
Parameters such as clock polarity and phase, baud rate, master mode operation, and transfer size are
determined by this register. The data output high impedance enable, DOHIE, controls the operation of
QSPI_Dout between data transfers. When DOHIE is cleared, QSPI_Dout is actively driven between
transfers. When DOHIE is set, QSPI_Dout assumes a high impedance state.
NOTE
Because the QSPI does not operate in slave mode, the master mode enable
bit, QMR[MSTR], must be set for the QSPI module to operate correctly.
15
14
13
10
9
8
7
0
Field
MSTR
DOHIE
BITS
CPOL CPHA
BAUD
Reset
0000_0001_0000_0100
R/W
Address
MBAR + 0x00A0
Figure 14-3. QSPI Mode Register (QMR)
Table 14-3. QMR Field Descriptions
Bits
Name
Description
15
MSTR
Master mode enable.
0 Reserved, do not use.
1 The QSPI is in master mode. Must be set for the QSPI module to operate correctly.
14
DOHIE
Data output high impedance enable. Selects QSPI_Dout mode of operation.
0 Default value after reset. QSPI_Dout is actively driven between transfers.
1 QSPI_Dout is high impedance between transfers.