參數(shù)資料
型號： MC68HC912BL16FU8
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP64
封裝： QFP-64
文件頁數(shù)： 9/128頁
文件大小： 532K
代理商： MC68HC912BL16FU8
MOTOROLA
MC68HC912BL16
106
MC68HC912BL16TS/D
The ATD control register 4 is used to select the clock source and set up the prescaler. Writes to the ATD
control registers initiate a new conversion sequence. If a write occurs while a conversion is in progress,
the conversion is aborted and ATD activity halts until a write to ATDCTL5 occurs.
S10BM — ATD 10-bit Mode Control
0 = 8 bit operation
1 = 10 bit operation
SMP1, SMP0 — Select Sample Time
These bits are used to select one of four sample times after the buffered sample and transfer has oc-
curred. Total conversion time depends on initial sample time (fixed at two ATD clocks), transfer time
(fixed at four ATD clocks), final sample time (programmable, refer to Table 34), and resolution time
(fixed at ten ATD clocks).
PRS4, PRS3, PRS2, PRS1, PRS0 — Select Divide-By Factor for ATD P-Clock Prescaler.
The binary value written to these bits (1 to 31) selects the divide-by factor for the modulo counter-based
prescaler. The P clock is divided by this value plus one and then fed into a
÷2 circuit to generate the
ATD module clock. The divide-by-two circuit insures symmetry of the output clock signal. Clearing these
bits causes the prescale value to default to one which results in a
÷2 prescale factor. This signal is then
fed into the
÷2 logic. The reset state divides the P clock by a total of four and is appropriate for nominal
operation between 2 MHz and 8 MHz bus rate. Table 35 shows the divide-by operation and the appro-
priate range of system clock frequencies.
Table 33 ATD Response to Background Debug Enable
FRZ1 FRZ0
ATD Response
0
Continue conversions in active background mode
0
1
Reserved
1
0
Finish current conversion, then freeze
1
Freeze when BDM is active
ATDCTL4 — ATD Control Register 4
$0064
Bit 7
6
5
4
3
2
1
Bit 0
S10BM
SMP1
SMP0
PRS4
PRS3
PRS2
PRS1
PRS0
RESET:
0
1
Table 34 Final Sample Time Selection
SMP1
SMP0
Final Sample Time
Total 8-bit Conversion Time
Total 10-bit Conversion Time
0
2 ATD clock periods
18 ATD clock periods
20 ATD clock periods
0
1
4 ATD clock periods
20 ATD clock periods
22 ATD clock periods
1
0
8 ATD clock periods
24 ATD clock periods
26 ATD clock periods
1
16 ATD clock periods
32 ATD clock periods
34 ATD clock periods
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