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參數(shù)資料
| 型號： | MC68HC912BL16FU8 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | QFP-64 |
| 文件頁數(shù)： | 35/128頁 |
| 文件大?。?/td> | 532K |
| 代理商： | MC68HC912BL16FU8 |
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MOTOROLA
MC68HC912BL16
14
MC68HC912BL16TS/D
Table 5 MC68HC912BL16 Signal Description Summary
Pin Name
Pin Number
Description
PW[3:0]
61–64
Pulse Width Modulator channel outputs.
ADDR[7:0]
DATA[7:0]
16–9
External bus pins share function with general-purpose I/O ports A and B. In sin-
gle chip modes, the pins can be used for I/O. In expanded modes, the pins are
used for the external buses.
ADDR[15:8]
DATA[15:8]
37–30
IOC[7], IOC[5:0]
7–1
Pins used for input capture and output compare in the timer and pulse accumu-
lator subsystem.
PAI
7
Pulse accumulator input
AN[7:0]
49–42
Analog inputs for the analog-to-digital conversion module
DBE
17
Data bus control and, in expanded mode, enables the drive control of external
buses during external reads.
MODB, MODA
18, 19
State of mode select pins during reset determine the initial operating mode of the
MCU. After reset, MODB and MODA can be configured as instruction queue
tracking signals IPIPE1 and IPIPE0 or as general-purpose I/O pins.
IPIPE1, IPIPE0
18, 19
ECLK
20
E-clock is the output connection for the external bus clock. ECLK is used as a
timing reference and for address demultiplexing.
RESET
23
An active low bidirectional control signal, RESET acts as an input to initialize the
MCU to a known start-up state, and an output when COP or clock monitor causes
a reset.
EXTAL
24
Crystal driver and external clock input pins. On reset all the device clocks are de-
rived from the EXTAL input frequency. XTAL is the crystal output.
XTAL
25
LSTRB
26
Low byte strobe (0 = low byte valid), in all modes this pin can be used as I/O. The
low strobe function is the exclusive-NOR of A0 and the internal SZ8 signal. (The
SZ8 internal signal indicates the size 16/8 access.)
TAGLO
26
Pin used in instruction tagging. See 16 Development Support.
R/W
27
Indicates direction of data on expansion bus. Shares function with general-pur-
pose I/O. Read/write in expanded modes.
IRQ
28
Maskable interrupt request input provides a means of applying asynchronous in-
terrupt requests to the MCU. Either falling edge-sensitive triggering or level-sen-
sitive triggering is program selectable (INTCR register).
XIRQ
29
Provides a means of requesting asynchronous non-maskable interrupt requests
after reset initialization.
BKGD
8
Single-wire background interface pin is dedicated to the background debug func-
tion. During reset, this pin determines special or normal operating mode.
TAGHI
8
Pin used in instruction tagging. See 16 Development Support.
CS/SS
57
Slave select output for SPI master mode, input for slave mode or master mode.
SCK
56
Serial clock for SPI system.
SDO/MOSI
55
Master out/slave in pin for serial peripheral interface
SDI/MISO
54
Master in/slave out pin for serial peripheral interface
TxD
53
SCI transmit pin
RxD
52
SCI receive pin
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