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| 型號(hào)： | MC68HC912BL16FU8 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | QFP-64 |
| 文件頁(yè)數(shù)： | 32/128頁(yè) |
| 文件大?。?/td> | 532K |
| 代理商： | MC68HC912BL16FU8 |
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MC68HC912BL16
MOTOROLA
MC68HC912BL16TS/D
127
in all modes. Tagging is disabled when BDM becomes active and BDM serial commands cannot be pro-
cessed while tagging is active.
TAGHI is a shared function of the BKGD pin.
TAGLO is a shared function of the PE3/LSTRB pin, a multiplexed I/O pin. For 1/4 cycle before and after
the rising edge of the E clock, this pin is the LSTRB driven output.
TAGLO and TAGHI inputs are captured at the falling edge of the E clock. A logic zero on TAGHI and/
or TAGLO marks (tags) the instruction on the high and/or low byte of the program word that was on the
data bus at the same falling edge of the E clock.
Table 46 shows the functions of the two tagging pins. The pins operate independently; the state of one
pin does not affect the function of the other. The presence of logic level zero on either pin at the fall of
ECLK performs the indicated function. Tagging is allowed in all modes. Tagging is disabled when BDM
becomes active and BDM serial commands are not processed while tagging is active.
The tag follows the information in the queue as the queue is advanced. When a tagged instruction
reaches the head of the queue, the CPU enters active background debugging mode rather than exe-
cuting the instruction. This is the mechanism by which a development system initiates hardware break-
points.
Table 46 Tag Pin Function
TAGHI
TAGLO
Tag
1
No Tag
1
0
Low Byte
0
1
High Byte
0
Both Bytes
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