參數(shù)資料
型號： MC68HC912BL16FU8
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP64
封裝： QFP-64
文件頁數(shù)： 26/128頁
文件大?。?/td> 532K
代理商： MC68HC912BL16FU8
MC68HC912BL16
MOTOROLA
MC68HC912BL16TS/D
121
This register can be read or written by BDM commands or firmware.
ENBDM — Enable BDM (permit active background debug mode)
0 = BDM cannot be made active (hardware commands still allowed)
1 = BDM can be made active to allow firmware commands
BDMACT — Background Mode Active Status
BDMACT becomes set as active BDM mode is entered so that the BDM firmware ROM is enabled and
put into the map. BDMACT is cleared by a carefully timed store instruction in the BDM firmware as part
of the exit sequence to return to user code and remove the BDM memory from the map. This bit has 4
clock cycles write delay.
0 = BDM not active; BDM ROM and registers are not in map
1 = BDM active and waiting for serial commands; BDM ROM and registers are in map
Care should be taken that the BDMACT bit is not unintentionally changed with the WRITE_NEXT firm-
ware command. If it is unintentionally changed from 1 to 0, it will cause a system runaway as it will dis-
able the BDM firmware ROM while the CPU12 is executing BDM firmware.The following two commands
show how BDMACT may unintentionally get changed from 1 to 0.
WRITE_X with data $FEFE
WRITE_NEXT with data $C400
The first command writes the data $FEFE to the X index register.The second command writes the data
$C4 to the $FF00 INSTRUCTION register and also writes the data $00 to the $FF01 STATUS register.
ENTAG — Instruction Tagging Enable
Set by the TAGGO instruction and cleared when BDM is entered. The serial system is disabled and the
tag function enabled 16 cycles after this bit is written.
0 = Tagging not enabled, or BDM active
1 = Tagging active (BDM cannot process serial commands while tagging is active.)
SDV — Shifter Data Valid
Shows that valid data is in the serial interface shift register. Used by BDM firmware.
0 = No valid data
1 = Valid Data
TRACE — Asserted by the TRACE1 instruction
100
D
101
X
110
Y
111
SP
STATUS — BDM Status Register
(BDM) $FF01
Bit 7
6
5
4
3
2
1
Bit 0
ENBDM
BDMACT
ENTAG
SDV
TRACE
0
RESET
01
NOTES:
1. ENBDM is set to 1 by the firmware in Special Single Chip mode.
1
0
Sp Sing Chip
& Peripheral
RESET:
0
All other modes
Table 42 REGN Decoding
REGN Value
Instruction
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