參數(shù)資料
型號(hào)： MC68HC912BL16FU8
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP64
封裝： QFP-64
文件頁數(shù)： 110/128頁
文件大?。?/td> 532K
代理商： MC68HC912BL16FU8
MOTOROLA
MC68HC912BL16
82
MC68HC912BL16TS/D
1 = Enable output drive reduction function
0 = Normal output drive capability
TCRE — Timer Counter Reset Enable
This bit allows the timer counter to be reset by a successful output compare 7 event.
0 = Counter reset inhibited and counter free runs
1 = Counter reset by a successful output compare 7
If TC7 = $0000 and TCRE = 1, TCNT will stay at $0000 continuously. If TC7 = $FFFF and TCRE = 1,
TOF will never get set even though TCNT will count from $0000 through $FFFF.
PR2, PR1, PR0 — Timer Prescaler Select
These three bits specify the number of
÷2 stages that are to be inserted between the module clock and
the timer counter.
The newly selected prescale factor will not take effect until the next synchronized edge where all pres-
cale counter stages equal zero.
TFLG1 indicates when interrupt conditions have occurred. To clear a bit in the flag register, write a one
to the bit.
Read anytime. Write used in the clearing mechanism (set bits cause corresponding bits to be cleared).
Writing a zero will not affect current status of the bit.
When TFFCA bit in TSCR register is set, a read from an input capture or a write into an output compare
channel ($90–$9F) will cause the corresponding channel flag CnF to be cleared.
C7F–C0F — Input Capture/Output Compare Channel “n” Flag.
TFLG2 indicates when interrupt conditions have occurred. To clear a bit in the flag register, set the bit
to one.
Read anytime. Write used in clearing mechanism (set bits cause corresponding bits to be cleared).
Any access to TCNT will clear TFLG2 register if the TFFCA bit in TSCR register is set.
TOF — Timer Overflow Flag
Set when 16-bit free-running timer overflows from $FFFF to $0000. This bit is cleared automatically by
Table 27 Prescaler Selection
PR2
PR1
PR0
Prescale
Factor
0
1
0
1
2
0
1
0
4
0
1
8
1
0
16
1
0
1
32
1
0
Reserved
1
Reserved
TFLG1 — Timer Interrupt Flag 1
$008E
Bit 7
6
5
4
3
2
1
Bit 0
C7F
C6F
C5F
C4F
C3F
C2F
C1F
C0F
RESET:
0
TFLG2 — Timer Interrupt Flag 2
$008F
Bit 7
6
5
4
3
2
1
Bit 0
TOF
0
RESET:
0
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