參數(shù)資料
型號： MC68HC912BL16FU8
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP64
封裝： QFP-64
文件頁數(shù)： 23/128頁
文件大?。?/td> 532K
代理商： MC68HC912BL16FU8
MC68HC912BL16
MOTOROLA
MC68HC912BL16TS/D
119
15.2.4 BDM Registers
Seven BDM registers are mapped into the standard 64-Kbyte address space when BDM is active. Map-
ping is shown in Table 40.
The content of the INSTRUCTION register is determined by the type of background command being
executed. The STATUS register indicates BDM operating conditions. The SHIFT register contains data
being received or transmitted via the serial interface. The ADDRESS register is temporary storage for
BDM commands. The CCRSAV register preserves the content of the CPU12 CCR while BDM is active.
The only registers of interest to users are the STATUS register and the CCRSAV register. The other
BDM registers are only used by the BDM firmware to execute commands. The registers are accessed
by means of the hardware READ_BD and WRITE_BD commands, but should not be written during
BDM operation (except the CCRSAV register which could be written to modify the CCR value).
The INSTRUCTION register is written by the BDM hardware as a result of serial data shifted in on the
BKGD pin. It is readable and writable in Special Peripheral mode on the parallel bus. It is discussed
here for two conditions: when a hardware command is executed and when a firmware command is
executed.
The INSTRUCTION register can be read or written in all modes. The hardware clears the INSTRUC-
TION register if 512 E-clock cycles occur between falling edges from the host.
The bits in the BDM instruction register have the following meanings when a hardware command is
executed.
H/F — Hardware/Firmware Flag
0 = Firmware instruction
1 = Hardware instruction
DATA — Data Flag
Indicates that data accompanies the command.
0 = No data
1 = Data included in command
R/W — Read/Write Flag
0 = Write
1 = Read
BKGND — Hardware request to enter active background mode
Table 40 BDM registers
Address
Register
$FF00
BDM Instruction Register
$FF01
BDM Status Register
$FF02–$FF03
BDM Shift Register
$FF04–$FF05
BDM Address Register
$FF06
BDM CCR Holding Register
INSTRUCTION — BDM Instruction Register (hardware command)
(BDM) $FF00
Bit 7
6
5
4
3
2
1
Bit 0
H/F
DATA
R/W
BKGND
W/B
BD/U
0
RESET:
0
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