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| 型號(hào)： | MC68HC912BL16FU8 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | QFP-64 |
| 文件頁(yè)數(shù)： | 61/128頁(yè) |
| 文件大小： | 532K |
| 代理商： | MC68HC912BL16FU8 |
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MOTOROLA
MC68HC912BL16
38
MC68HC912BL16TS/D
This register controls the operation of the Flash EEPROM array. BOOTP cannot be changed when the
LOCK control bit in the FEELCK register is set or if ENPE in the FEECTL register is set.
BOOTP — Boot Protect
The boot block is located at $7800–$7FFF or $F800–$FFFF depending upon the mapped location of
the Flash EEPROM array.
0 = Enable erase and program of 2-Kbyte boot block
1 = Disable erase and program of 2-Kbyte boot block
In normal mode, writes to FEETST control bits have no effect and always read zero. The Flash
EEPROM module cannot be placed in test mode inadvertently during normal operation.
FSTE — Stress Test Enable
0 = Disables the gate/drain stress circuitry
1 = Enables the gate/drain stress circuitry
GADR — Gate/Drain Stress Test Select
0 = Selects the drain stress circuitry
1 = Selects the gate stress circuitry
HVT — Stress Test High Voltage Status
0 = High voltage not present during stress test
1 = High voltage present during stress test
FENLV — Enable Low Voltage
0 = Disables low voltage transistor in current reference circuit
1 = Enables low voltage transistor in current reference circuit
FDISVFP — Disable Status VFP Voltage Lock
When the VFP pin is below normal programming voltage the Flash module will not allow writing to the
LAT bit; the user cannot erase or program the Flash module. The FDISVFP control bit enables writing
to the LAT bit regardless of the voltage on the VFP pin.
0 = Enable the automatic lock mechanism if VFP is low
1 = Disable the automatic lock mechanism if VFP is low
VTCK — VT Check Test Enable
When VTCK is set, the Flash EEPROM module uses the VFP pin to control the control gate voltage; the
sense amp time-out path is disabled. This allows for indirect measurements of the bit cells program and
erase threshold. If VFP < VZBRK (breakdown voltage) the control gate will equal the VFP voltage.
If VFP > VZBRK the control gate will be regulated by the following equation:
Vcontrol gate = VZBRK + 0.44 × (VFP VZBRK)
0 = VT test disable
1 = VT test enable
STRE — Spare Test Row Enable
The spare test row consists of one Flash EEPROM array row. The reserved word at location 31 contains
production test information which must be maintained through several erase cycles. When STRE is set,
the decoding for the spare test row overrides the address lines which normally select the other rows in
the array.
FEETST — Flash EEPROM Module Test Register
$00F6
Bit 7
6
5
4
3
2
1
Bit 0
FSTE
GADR
HVT
FENLV
FDISVFP
VTCK
STRE
MWPR
RESET:
0
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