參數(shù)資料
型號(hào)： MC68HC912BL16FU8
廠(chǎng)商： MOTOROLA INC
元件分類(lèi)： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP64
封裝： QFP-64
文件頁(yè)數(shù)： 106/128頁(yè)
文件大小： 532K
代理商： MC68HC912BL16FU8
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MC68HC912BL16
MOTOROLA
MC68HC912BL16TS/D
79
Read or write anytime.
NOTE
Port T[6] is not bonded to any pin in MC68HC912BL16.
The bits of OC7D correspond bit-for-bit with the bits of timer port (PORTT). When a successful OC7
compare occurs, for each bit that is set in OC7M, the corresponding data bit in OC7D is stored to the
corresponding bit of the timer port.
When the OC7Mn bit is set, a successful OC7 action will override a successful OC[6:0] compare action
during the same cycle; therefore, the OCn action taken will depend on the corresponding OC7D bit.
A full access for the counter register should take place in one clock cycle. A separate read/write for high
byte and low byte will give a different result than accessing them as a word.
Read anytime.
Write has no meaning or effect in the normal mode; only writable in special modes (SMODN = 0).
The period of the first count after a write to the TCNT registers may be a different size because the write
is not synchronized with the prescaler clock.
Read or write anytime.
TEN — Timer Enable
0 = Disables the timer, including the counter. Can be used for reducing power consumption.
1 = Allows the timer to function normally.
If for any reason the timer is not active, there is no
÷64 clock for the pulse accumulator since the E÷64
is generated by the timer prescaler.
TSWAI — Timer Stops While in Wait
0 = Allows the timer to continue running during wait.
1 = Disables the timer when the MCU is in the wait mode. Timer interrupts cannot be used to get
the MCU out of wait.
TSBCK — Timer Stops While in Background Mode
0 = Allows the timer to continue running while in background mode.
1 = Disables the timer whenever the MCU is in background mode. This is useful for emulation.
TFFCA — Timer Fast Flag Clear All
0 = Allows the timer flag clearing to function normally.
OC7D — Output Compare 7 Data Register
$0083
Bit 7
6
5
4
3
2
1
Bit 0
OC7D7
OC7D6
OC7D5
OC7D4
OC7D3
OC7D2
OC7D1
OC7D0
RESET:
0
TCNT — Timer Count Register
$0084–$0085
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
14
13
12
11
10
9
Bit 8
Bit 7
6
5
4
3
2
1
Bit 0
RESET:
0
TSCR — Timer System Control Register
$0086
Bit 7
6
5
4
3
2
1
Bit 0
TEN
TSWAI
TSBCK
TFFCA
0
RESET:
0
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