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參數(shù)資料
| 型號： | MC68HC05CJ4FB |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | PLASTIC, QFP-44 |
| 文件頁數(shù)： | 79/114頁 |
| 文件大?。?/td> | 4047K |
| 代理商： | MC68HC05CJ4FB |
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GENERAL RELEASE SPECIFICATION
SLAVE-ONLY M-BUS
MC68HC(7)05CJ4
10-2
Rev. 2.1
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and the first bit of the slave's address (already in the shifter) is shifted out. These
two address bits are compared and if a match occurs, a counter is incremented. If
a match does not occur, the counter is not incremented. This continues for the
duration of the seven bits of address. After the eighth clock pulse, the shift register
stops shifting. The SMF bit is set after the ninth clock pulse.
10.2.3 After the First Reception
When SMF is set, an interrupt request is generated to the CPU based on the
following conditions:
A START condition was recently detected.
The address match counter equals seven
SMIE is set
If the address match counter is less than seven, this means that the slave is not
being addressed. In that case, the start condition and SMF are cleared and the
SCL input is disabled. The SOMB will ignore all further clock pulses until a
subsequent start condition is detected.
If a start condition was not detected on this transmission, then the address match
counter is ignored and the data is treated as data.
If the address is matched and the start was detected, the acknowledge is
accomplished by forcing the SDA line low (in hardware) and enabling the ninth-bit
detector on the clock line. When the ninth clock pulse is detected on the clock line,
the SDA line is released automatically and the SCL line is forced low to stretch the
clock. When the serial service routine is completed, the user must release the
clock line by writing a '0' to CLKR. This serves as a mechanism for releasing the
clock.
NOTE
The M-bus address/data register (MBADR) now has the received
data and bit zero contains the R/W bit from the master. This should
be checked in software and the T/R bit in the slave should be set
accordingly.
The SOMB is now enabled and prepared to receive further data. It will stay in this
mode until another start condition is detected, at which time this process will begin
again.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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