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參數(shù)資料
| 型號： | MC68HC05CJ4FB |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | PLASTIC, QFP-44 |
| 文件頁數(shù)： | 56/114頁 |
| 文件大?。?/td> | 4047K |
| 代理商： | MC68HC05CJ4FB |
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GENERAL RELEASE SPECIFICATION
SERIAL COMMUNICATIONS INTERFACE
Rev. 2.1
8-9
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In example 7, the majority of the logic sense samples taken at RT8, RT9, and RT10
during the start bit time were high, suggesting that the logic sense should be one
but recall that, for the start bit time only, the logic sense indicated by the RT8, RT9,
and RT10 samples is overridden to zero.
Figure 8-7. Start Search Example 7
To understand why start bit times do not obey the majority sampling of RT8, RT9,
and RT10, consider what would happen if the start bit noise shown in example 7
occurred at a time when the sum of logic sense one bit times at the end of the
preceding frame and the number of logic sense one bit times at the beginning of
this frame was greater than the number of bits in a frame. The wake-up logic would
erroneously wake up a receiver that did not force the start bit to be seen as a zero.
Also, consider that in order for the start bit to have been recognized, at least three
of the samples taken at RT1, RT3, RT5, and RT7 had to be lows. Even if two of the
samples taken at RT8, RT9, and RT10 were high, then there would still be a
majority of all samples taken during the start bit time in favor of a logic zero
decision.
*RT1
RT1
RT2
RT3
RT4
RT5
RT6
RT7
RT8
RT9
RT10
RT11
RT12
RT13
RT14
RT15
RT16
*RT1
RT2
RT3
11
1
10
0
1
0
PERCEIVED START BIT
ACTUAL START BIT
LSB
* = RESTART RT CLOCK
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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