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| 型號(hào)： | MC68HC05CJ4FB |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | PLASTIC, QFP-44 |
| 文件頁(yè)數(shù)： | 34/114頁(yè) |
| 文件大?。?/td> | 4047K |
| 代理商： | MC68HC05CJ4FB |
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GENERAL RELEASE SPECIFICATION
INTERRUPTS
Rev. 2.1
4-3
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4.3 Software Interrupt (SWI)
The SWI is an executable instruction and a non-maskable interrupt: It is executed
regardless of the state of the I bit in the CCR. If the I bit is zero (interrupts enabled),
SWI executes after interrupts which were pending when the SWI was fetched, but
before interrupts generated after the SWI was fetched. The interrupt service
routine address is specified by the contents of memory locations $1FFC and
$1FFD.
4.4 External Interrupt
If the interrupt mask bit (I bit) of the CCR is set, all maskable interrupts (internal and
external) are disabled. Clearing the I bit enables interrupts. The interrupt request
is latched immediately following the falling edge of IRQ. It is then synchronized
internally and serviced as specified by the contents of $1FFA and $1FFB.
Either a level-sensitive and edge-sensitive trigger, or an edge-sensitive-only trigger
operation is selectable by writing to bit 3 of the T2CSR register.
NOTE
The internal interrupt latch is cleared in the first part of the interrupt
service routine; therefore, one external interrupt pulse could be
latched and serviced as soon as the I bit is cleared.
4.5 Timer 1 Interrupt
There are three different timer interrupt flags that cause a timer interrupt whenever
they are set and enabled. The interrupt flags are in the timer status register (TSR),
and the enable bits are in the timer control register (TCR). Any of these interrupts
will vector to the same interrupt service routine, located at the address specified by
the contents of memory location $1FF8 and $1FF9.
4.6 SCI Interrupt
There are five different SCI interrupt flags that cause an SCI interrupt whenever
they are set and enabled. The interrupt flags are in the SCI status register (SCSR),
and the enable bits are in the SCI control register 2 (SCCR2). Any of these
interrupts will vector to the same interrupt service routine, located at the address
specified by the contents of memory location $1FF6 and $1FF7.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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