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參數(shù)資料
| 型號(hào)： | MC68HC05CJ4FB |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | PLASTIC, QFP-44 |
| 文件頁(yè)數(shù)： | 58/114頁(yè) |
| 文件大?。?/td> | 4047K |
| 代理商： | MC68HC05CJ4FB |
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GENERAL RELEASE SPECIFICATION
SERIAL COMMUNICATIONS INTERFACE
Rev. 2.1
8-11
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position in R8 at the same time the lower 8 bits of data are transferred from the
receive serial shift register to SCDR.
The last bit to be shifted in for each frame is the stop bit, which should be a logic
one. If a logic zero bit time is sensed where a stop bit was expected, it is called a
Framing Error. The framing error is usually caused by mismatched baud rates
between the transmitter and receiver, or by noise that caused the start bit to be
missed so that the frame was synchronized incorrectly. It should be noted that it is
possible for a framing error to go undetected because there is a chance that the
data sampled where the stop bit was expected could have been a logic one
anyway.
When the stop bit is received, the frame is considered to be complete and the
received character in the receive serial shift register is normally transferred in
parallel to the receive data register (RDR). Several other actions occur at the same
time this transfer is taking place. The abnormal case where the RDRF flag in the
SCSR register is set at the time the transfer was to occur is called an overrun
because a new data character was received from the serial line before a previously
received character was serviced by the CPU. No transfer to RDR is allowed while
RDRF or OR is set. Parallel transfers and associated actions to status bits occur
at a time that will not interfere with CPU access to the affected registers.
All status flags associated with a serially received frame are simultaneously set.
When a complete frame has been serially received either the receive data register
full (RDRF) or the over run (OR) status flag always will be set. When the receive
interrupt enable (RIE) control bit in the SCCR2 register is set to one, a hardware
interrupt request will result if either RDRF or OR is set indicating reception of a new
frame of data. The receive status bits noise flag (NF) and framing error (FE) do not
separately cause hardware interrupts because they are never set without being
accompanied by RDRF. The NF and FE flags are always associated with the data
in the RDR so they never get set with OR but do get set with RDRF if the associated
frame had the corresponding error(s).
An automatic clearing mechanism is associated with the receiver status bits. The
mechanism involves reading the SCSR register followed by reading the RDR
register (SCDR — read). When the RDR is read, any of the receive status bits
(RDRF, IDLE, OR, NF, or FE) that were set when the SCSR register was read will
automatically be cleared.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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