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| 型號： | MC68HC05CJ4FB |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | PLASTIC, QFP-44 |
| 文件頁數(shù)： | 72/114頁 |
| 文件大小： | 4047K |
| 代理商： | MC68HC05CJ4FB |
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GENERAL RELEASE SPECIFICATION
SERIAL PERIPHERAL INTERFACE
Rev. 2.1
9-3
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9.2.4 Slave Select (SS)
In slave mode, the slave select (SS input) is generated by the master (parallel port
may be used) and used to “enable one” of several slaves to accept and/or return
data or “enable several” slaves to accept data. To insure a data byte transfer, the
SS signal must be low prior to occurrence of SCK1 and must not become high until
after the 8th (last) SCK1 cycle. Figure 9-2 shows the clock (SCK1) and data
relationship. Depending on the state of the CPHA control bit, the SS pin pulled low:
(1) allows the first bit of data onto the MISO system line for transfer and (2)
prevents the slave from reading or writing the data register. A further description of
the effect of the (SS) pin and (CPHA) control bit on the I/O data register is given in
the description of the (WCOL) status flag. The (WCOL) flag warns the slave if it has
had a conflict between a transmission and a write of the data register. A high level
on SS forces MISO to the high-impedance state. Also, SCK1 and MOSI are
ignored by the disabled slave.
In master mode, slave select (SS) input is monitored to assure that it stays false
(high). If slave select becomes true, the device immediately exits the master mode
and becomes a slave (MSTR = 0). Also, control bit (SPE) is forced to a zero
causing all SPI system pins to be inputs. An interrupt flag (MODF) is set warning
the device that the above events have occurred. The significance of this is that a
collision has occurred; that is, two devices have both become masters. This is
normally the result of software error, although some systems may allow the default
master to “knock all other masters off the bus” if an erroneous bus state is detected.
This is, of course, a catastrophic event and it is the responsibility of the default
master to completely “clean up” the system.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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