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| 型號： | MC68HC05CJ4FB |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | PLASTIC, QFP-44 |
| 文件頁數(shù)： | 32/114頁 |
| 文件大?。?/td> | 4047K |
| 代理商： | MC68HC05CJ4FB |
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GENERAL RELEASE SPECIFICATION
INTERRUPTS
Rev. 2.1
4-1
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SECTION 4
INTERRUPTS
4.1 Introduction
The MCU can be interrupted seven different ways: the six maskable hardware
interrupts (IRQ, SCI, SPI, I2C, timer 1, and timer 2) and the non-maskable software
interrupt instruction (SWI).
Interrupts cause the processor to save register contents on the stack and to set the
interrupt mask (I bit) to prevent additional interrupts. The RTI instruction causes the
register contents to be recovered from the stack and normal processing to resume.
Unlike RESET, hardware interrupts do not cause the current instruction execution
to be halted, but are considered pending until the current instruction is complete.
NOTE
The current instruction is the one already fetched and being operated
on.
When the current instruction is complete, the processor checks all pending
hardware interrupts. If interrupts are not masked (CCR I bit clear) and if the
corresponding interrupt enable bit is set, the processor proceeds with interrupt
processing; otherwise, the next instruction is fetched and executed.
The SWI is executed the same as any other instruction, regardless of the I-bit state.
See Table 4-1 for more information.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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