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參數(shù)資料
| 型號(hào)： | MC68HC05CJ4FB |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | PLASTIC, QFP-44 |
| 文件頁(yè)數(shù)： | 57/114頁(yè) |
| 文件大?。?/td> | 4047K |
| 代理商： | MC68HC05CJ4FB |
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GENERAL RELEASE SPECIFICATION
SERIAL COMMUNICATIONS INTERFACE
MC68HC(7)05CJ4
8-10
Rev. 2.1
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8.3.2 Receiver Functional Operation
This receiver includes a receive serial shift register and a parallel receive data
register (This is called a double buffered system because after a complete
character is shifted in serially it is immediately moved to a parallel register so that
the subsequent character can be shifted in without requiring the CPU to
immediately service the first character.). The receive serial shift register is internal
to the receive logic and may not be read or written directly by the CPU. The input
of this serial shifter is connected to the majority sampling logic of the front end.
The receiver can operate in either of two formats as specified by the M control bit
in the SCCR1 register. The most common standard word format for NRZ serial
communication is one start bit (logic zero or space) followed by eight data bits (LSB
first) followed by one stop bit (logic one or mark). In addition to this standard format
this circuit provides hardware for a nine data bit format as follows: one start bit,
eight data bits (LSB first), ninth data bit, and one stop bit. If the nine data bit mode
is selected, software control (and overhead) of the ninth bit may be used to support
a number of special formats. The ninth data bit is positioned as R8 in the SCCR1
register. Some examples of its use include:
start, eight data, two stop bits
start, eight data, parity, one stop
w/ odd, even, mark, or space parity
start, seven data, parity, two stop bits
w/ odd, even, mark, or space parity
start, eight data, address/control, one stop bit
where address/control bit identifies special command words
The receive logic is enabled when the receive enable (RE) bit in the SCCR2
register is set to one. When RE is zero the receive logic is initialized and most of
the receiver front end logic is disabled. The receiver front end logic drives a state
machine (running off the RT clock) and provides the derived logic level for each bit
time. This state machine controls when the front end logic is to sample the RXD pin
and controls when data is to be passed to the receive serial shift register. Data is
shifted into the receive serial shift register according to the most recent
synchronization of the RT clock. From this point on in the discussion, data
reception may be considered to be synchronous.
The logic sense of each bit in the frame is determined from the majority of three
samples taken near the middle of the bit time except the start bit which is forced to
be shifted in as a zero regardless of the result of the majority sampling logic (see
the discussion of the receiver front end logic). The next eight bits shifted in are the
basic data byte (LSB is shifted in first). The next bit shifted in depends on the mode
selected by the M bit in SCCR2. If the nine data bit format is selected, the next bit
received after the MSB is the ninth data bit. It will be transferred to its appropriate
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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